September 1-5, 2025

Registration deadline: August 1, 2025
Payment deadline: August 22, 2025

Download one-page schedule here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, September 1

TUESDAY, September 2

WEDNESDAY, September 3

THURSDAY, September 4

FRIDAY, September 5

Integrated System Design in 5nm Era
September 1-5, 2025
EPFL Premises, Lausanne, Switzerland

The rapid growth of Artificial Intelligence (AI) and the Internet of Things (IoT), combined with the end of Moore’s Law, is transforming society and industry. Indeed, to sustain our growth with AI and IoT, new hardware architectures and methodologies for designing and optimizing complex integrated systems are needed to exploit the latest nanoscale technologies.

Moreover, the future is even more challenging, with the emergence of AI at the Edge requiring dedicated, sustainable, energy-efficient electronic hardware. Billions of autonomous systems at the Edge are foreseen to feature increased intelligence under a constrained amount of energy, high heterogeneity in technology integration, and a complex packaging and large memory capacity. These systems are critical enablers of future Industry 4.0, autonomous cars, robots, personalized and preventive healthcare, and environmental monitoring for smart cities and a smarter planet.

This course addresses the aforementioned challenges of designing the next generation of digital systems in a highly multidisciplinary manner. It proposes a complete program to understand nanoscale integrated systems’ latest technologies, architectures, and design flows. Lectures will start by covering the progress in nanoscale technologies for computation and storage, with a particular focus on chiplet-based or 2.5D, 3D stacked system design and monolithic integration to boost density and lower wiring congestion by exploiting the vertical dimension. Then, it will include a complete coverage of new open-source computing architectures inspired by the brain’s adaptive information processing and the latest design flows using high-level synthesis (HLS) languages. Next, new open-source hardware architectures and co-design flows will be presented to integrate diverse computing accelerators (like in-memory, systolic arrays, and coarse-grained reconfigurable accelerators) with single- and multi-core system-in-chip architectures. The course will conclude by presenting new design flows to build CMOS circuits using nanosheets and exploiting analog vs digital in-memory computing. On Wednesday, it will include a hands-on session.

This course is part of a successful series of short weeklong courses focused on various aspects of integrated circuit design intended primarily for industry. They have been offered by Mead Education (https://mead.ch/mead/) since 1999, and typically take place at the campus of EPFL (Lausanne, Switzerland), although some virtual courses have been offered since the pandemic.

Trends in Digital Design and Design Methodologies (2 lectures)
Jan Rabaey, UC Berkeley, USA

Digital logic is an essential part of every mixed-signal system-on-a-chip solution. With continued scaling of CMOS technology and the integration of more and more functionality, it has become an ever-important part. Addressing the resulting increase in complexity, caused both by technology and functionality, requires revisiting the prevailing design methodologies. While an in-depth overview in emerging trends is hard in a two-lecture sequence, we will outline some of the major trends and techniques.

Evolution in Digital CMOS Technology and its Impact on Design
Jan Rabaey, UC Berkeley, USA

CMOS technology has continued scaling at a pace set by Moore’s law. However, the nature of that scaling has changed substantially over the past decade. The minimum length of a transistor has pretty much plateaued around 12-13 nm. What has continued increasing is the density (transistors/mm2). This further into an increase in performance and energy efficiency, albeit at a slower pace than before. In this presentation, we will discuss these scaling trends, how they are being accomplished, and how they may extend into the future. We further elaborate on how these developments impact the way digital circuits are designed, optimized and verified.

Design Methodologies for Systems-on-a-Chip
Jan Rabaey, UC Berkeley, USA

Digital circuits are becoming exceedingly complex and now feature many billions of transistors. The most advanced systems-on-a-chip combine a broad range of processors (CPU, GPU), accelerators and neural processors, dedicated memory systems, networks-on-a-chip and fast input-output interfaces. Designing integrated systems of this complexity requires an evolution in design methodology, using higher levels of abstraction and more complicated building blocks. Yet, little of this is reflected in the design flows offered by the major EDA vendors today. This lecture will elaborate on how some of the emerging ideas on how design flows could evolve, including public domain components such as RISC-V, open flows and higher abstraction levels.

New Open-Source HW (Single and Multi-Core) Platforms for AI/ML
Frank K. Gurkaynak, ETHZ, Switzerland

In this lecture, based on the experience of the Parallel Ultra Low Power (PULP) platform project, I will explain the principles that we followed to obtain energy-efficient computing architectures that span a wide range of applications from simpler edge-IoT processors to hardware accelerators for demanding data-centric workloads. All presented architectures have been developed as open-source projects and are available using a permissive license. We will discuss the motivations and how this open-source approach has helped our innovations as well.

New Accelerator-Based Open-Source Hardware and Co-Design Flows
David Atienza, EPFL, Switzerland

This session will discuss novel co-design flows to effectively conceive the next generation of edge AI computing architectures in nano-scale technologies by taking inspiration from how the brain processes incoming information and adapts to changing conditions. In particular, these novel edge AI architectures include two key concepts. First, it exploits the idea of exploiting computing inexactness at the system level to integrate multiple computing accelerators at the hardware level for higher energy efficiency. Second, these edge AI architectures can operate ensembles of neural networks at the software level to improve machine learning (ML) and Deep Learning (DL) outputs robustness at system level, while minimizing memory footprint for the target final application. These two concepts have enabled the creation of new open-source hardware platforms, such as the eXtended and Heterogeneous Energy-Efficient Hardware Platform (called X-HEEP). X-HEEP will be showcased in this presentation to effectively create commercial edge AI systems for different healthcare applications.

The Open-Source Hardware Ecosystem: Current State and Future Prospects
Davide Schiavone, OpenHW Group, Switzerland

Open-Source Hardware (OSH) is a key revolution in the technology landscape, democratizing access to hardware design and fostering innovation through collaboration. This lecture will explore the current state of the OSH ecosystem, examining its key members, the technology-readiness level of the projects, and the community’s impact. We will delve into the successes and challenges faced by OSH initiatives, highlighting key developments that have propelled the movement forward.
As we look to the future, the lecture will discuss potential trajectories for OSH, including heterogeneous systems ranging from ultra-low-power to high-performance SoCs.

New Memory Technologies (3D Stacking, Ultra-Low Power, etc.)
Andreas Burg, EPFL, Switzerland

Any form of computing both in data centers and at the edge always involves both logic as well as memory. While logic has rapidly advanced providing higher density, greater speed, and better energy efficiency with each technology generation, it has also become clear that memory and memory access is now the performance limiting factor. This limitation is known as the memory wall. Large amounts of data (as required for example for AI) must often be stored separately from the compute die, which comes at very high penalty for latency and energy per access. Large on-chip caches mitigate the resulting memory bottleneck, but consume quickly a dominant portion of the compute-die area and power, leading to high cost and limited cache capacity. What makes this situation worse is fact that on-chip memories have stopped scaling at the 5nm node. In fact, a 5nm bitcell is only about 25% smaller compared to a 7nm bitcell and the bitcell size in 2nm can be even larger than its counter part in 5nm. The reason for this trend is the fact that design-technology co-optimization (DCTO) has almost exclusively focused on the continuation of scaling for logic, neglecting the impact on the so important on-chip memories.
In this presentation, I will discuss the memory wall and the latest portfolio of solutions for efficiently storing and accessing data for different system requirements. We will consider the imminent limitations and challenges of on-chip memories associated with scaled technology nodes and corresponding solutions and emerging technologies. I will further review the technologies and trends for realizing and connecting high-density large-scale off-chip random access memory with sufficient bandwidth and good energy efficiency using 2.5D and 3D integration.

High-Level Synthesis for Optimal and Fast Design of Digital Systems
Nanni De Micheli, EPFL, Switzerland

High-level synthesis is a method for transforming models of circuits and systems into an interconnection of modules that implement a data path and a related control unit that executes the operations on the data path. Models are usually expressed in a hardware description language and are first transformed into a set of representative graphs. Scheduling and resource sharing assign then a temporal and spatial dimension to the graphs, thus determining when operations execute and which hardware resource implements each operation. High-level synthesis tools enable designers to quickly map high-level models into circuit structures, determine the series/parallel execution of the operation, thus optimizing latency and hardware resources. Users benefit from high-level synthesis tools by reducing design time, and thus improving their productivity, which is essential for nanometer-scale design. This methodology is particularly helpful to design hardware accelerators for specific functions.

HANDS-ON Developing and Testing Heterogeneous Accelerator-Based Platforms
David Atienza, EPFL, Switzerland

This session (including hands-on exercises and demos) presents the new hardware-software co-design techniques to develop heterogeneous multi-core embedded systems including specialized hardware accelerators in latest technology nodes. The hands-on exercises will be developed using FPGAs and will present how to construct complex multi-core architectures including hardware accelerators described with high-level synthesis tools (HLS) that reduce total execution time and energy consumption for complex tasks. Also, it will cover how to perform fine-grained optimizations in HLS: loops, arrays, memory accesses and scheduling to optimize the final generated hardware, as well as coarse-grained optimizations in HLS: dataflow model, tasks and scheduling to create parallel hardware workers to effectively exploit software parallelization. Finally, this session will explain how to accurately measure performance at system-level, as well as how to perform simulation and on-chip debugging for complete multi-core heterogeneous platforms.

The Future of Computing Hardware through Heterogeneous 3D Integration: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design
Subhasish Mitra, Stanford, USA

The computation demands of 21st-century abundant-data workloads, such as AI/Machine Learning, far exceed the capabilities of today’s computing systems. The next leap in computing performance requires the next leap in integration. Just as integrated circuits brought together discrete components, this next level of integration must seamlessly fuse disparate parts of a system – e.g., compute, memory, inter-chip connections – synergistically for large energy and throughput benefits. Transformative NanoSystems exploit unique characteristics of nanotechnologies for new chip architectures through ultra-dense 3D integration of logic and memory – the N3XT 3D approach. Multiple N3XT 3D chips are integrated through a continuum of chip stacking/interposer/wafer-level integration — the N3XT 3D MOSAIC — to scale with growing problem sizes. Several hardware prototypes, built in industrial facilities resulting from lab-to-fab activities, demonstrate the effectiveness of our approach. We target 1,000X system-level Energy-Delay-Product benefits, especially for abundant-data workloads.

Design and System Technology Co-Optimization Beyond 5nm CMOS
Julien Ryckaert, IMEC, Belgium

In this lecture we will dive into the mechanisms that enable the scaling of technologies in the nm CMOS era. Indeed, beyond the 20nm node, miniaturization alone could not provide an overall system PPA scaling anymore and needed to be assisted by a careful design and system centric approach to technology research. This has led to the so-called Design-Technology Co-Optimization (DTCO) framework. Nowadays, it is accepted that more than 50% of scaling is driven by DTCO. As we scale further we need to enrich our understanding of how technology impacts circuits and systems and in some cases pushes problems to be studied at system level in actual workload conditions. This evolution is referred to as System-Technology Co-Optimization (STCO) and is expected to drive scaling further deep into the angstrom era. This lecture will explain this evolution and describe the various methods put in place to enable DTCO and STCO. We will explore how these frameworks have impacted the course of technology scaling and extrapolate these into the future of scaling.

Neuro-Vector-Symbolic Architectures: An Algorithmic-Hardware Framework Towards Artificial General Intelligence
Abbas Rahimi, IBM, Switzerland

Emerging neuro-symbolic AI approaches display both perception (System I) and reasoning (System II) capabilities, but inherit the limitations of their individual deep learning and classical symbolic AI components. By synergistically combining neural networks and machinery of vector-symbolic architectures, we propose the concept of neuro-vector-symbolic architecture (NVSA). NVSA exploits its powerful operators on high-dimensional composable distributed representations that serve as a common language between neural nets and symbolic AI. We elaborate how NVSA can solve challenging tasks such as few-shot continual learning, visual abstract reasoning, and computationally hard problems (e.g., factorization of perceptual representations, or exhaustive searches involved in abstract reasoning) faster and more accurately than other state-of-the-art methods. Further, we show how efficient realization of NVSA can be informed and benefitted by the physical properties of analog in-memory computing hardware, including O(1) matrix-vector-multiplications, in-situ progressive crystallization, and intrinsic stochasticity of phase-change memory devices.

Overview of Various System-Level Industrial Case Studies Designs
David Atienza, EPFL, Switzerland

The session will cover the major challenges and requirements for the design of different industial case studies based on AI/ML systems. Classical hardware design concepts, such as accuracy, cost, validation or design exploration time have evolved in the new AI/ML era and are drive which hardware systems are used in different industrial applications. These concepts will be illustrated with examples of latest edge AI systems for home automation and healthcare systems.

June 17-21, 2024

Registration deadline: May 17, 2024
Payment deadline: June 7, 2024

Download One-Page Schedule Here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 17

TUESDAY, June 18

WEDNESDAY, June 19

THURSDAY, June 20

FRIDAY, June 21

Low-Power Analog Circuit Design
June 17-21, 2024
EPFL Premises, Lausanne, Switzerland

MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design
Christian Enz, EPFL

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.

Design of Low-power Analog Circuits using the Inversion Coefficient
Christian Enz, EPFL

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.

Noise Performance of Elementary Circuit Blocks
Boris Murmann, University of Hawaii

Designing energy-energy efficient analog circuits requires a solid understanding of electronic noise. The material covered in these two modules requires no prerequisite knowledge and looks at shot noise (due to discreteness as charge) as an intuitive baseline for further treatment. After modeling thermal and 1/f noise at the device level, we analyze its impact on elementary circuits such as common source/gate/drain amplifiers as well as switched capacitor structures. We then expand the treatment to feedback circuits with an emphasis on sensor front ends. Lastly, we analyze noise in filters and the noise penalty paid for emulating inductors using active circuits.

Opamp Topologies and Design Fundamentals
Boris Murmann, University of Hawaii

While there exist a myriad of topologies and design tricks for integrated opamps, these two introductory modules intend to untangle the design space with an emphasis on the fundamentals. Covered topics will include: (1) Elementary building blocks operated at low supply voltage and/or low current: Current mirrors, differential pairs, inverter-based stages, low-voltage cascode configurations; (2) Basic topologies: Telescopic, folded-cascode, and multi-stage; (3) Stability and frequency compensation techniques; (4) fully differential implementation and common-mode feedback.

Low-Power High Efficiency OpAmp Design
Klaas Bult, Analog Design Consult

The goal of this lecture is to find the relationship between circuit performance and power dissipation. As an example, a commonly-used OpAmp is analysed and expressions are found that give detailed insight into what power dissipation is needed to obtain a certain performance. The result is simple expression that show power dissipation as a function of performance parameters.

Low-Power High Efficiency Residue Amplifiers
Klaas Bult, Analog Design Consult

In the past 1.5 decade, residue amplifiers have shown a remarkable 50-fold reduction in power dissipation. The findings of the previous lecture are being used to explain this reduction, through a step-by-step analysis that details which circuit techniques enabled this power reduction.

Analog Design Methodology and Practical Techniques for Frequency Compensation
Vadim Ivanov, Texas Instruments

Abstract.

Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources
Vadim Ivanov, Texas Instruments

Discussed are principles of the voltage reference generation, primarily of the bandgap voltage references, its error sources and techniques for improving accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; layout and packaging; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption. Considered are biasing cores, power-on resets, design of the mirror trees and circuit techniques for current source generation with high impedance and wide voltage range.

Power Dissipation in ADC Buidling Blocks
Klaas Bult, Analog Design Consult

Choosing the correct ADC architecture is the most powerful means to obtain low power dissipation. Finding expressions for the power dissipation of all ADC building blocks, is a first step in that direction. Using the same technique described in the lecture “Low Power High Efficiency OpAmp Design”, the most common ADC building block are analysed and expressions are found for power dissipation, as a function of their performance parameters.

Power Dissipation in ADCs
Klaas Bult, Analog Design Consult

This lecture builds on the findings of the lecture “Power Dissipation in ADC Building Blocks” and uses the results found in that lecture to come to estimations of power dissipation of various kinds of ADC architectures, dependent on their performance. A comparison is made between these estimates and the results that can be found in published results.

Micropower ADCs
Kofi Makinwa, TU Delft

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Energy Efficient Sensor Interfaces
Taekwang Jang, ETHZ

Abstract.

Low-Power Frequency Reference Circuits
Taekwang Jang, ETHZ

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
In this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.

Power Management With Nanoampere Consumption and Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments

Abstract.

June 17-21, 2024

Registration deadline: May 17, 2024
Payment deadline: June 7, 2024

Downloard one-page schedule here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 17

TUESDAY, June 18

WEDNESDAY, June 19

THURSDAY, June 20

FRIDAY, June 21

Practical Design of Data Converters
June 17-21, 2024
EPFL Premises, Lausanne, Switzerland

Basic ADC Topologies and Specifications: Overview
Marcel Pelgrom, Pelgrom Consult, The Netherlands

After an introduction in the fundamental limits given by timing and component accuracy, the basic architectures of ADCs and DACs are reviewed and the main characteristics indicated. A glossary of specification definitions is presented along with practical tips to evaluate these specifications.

ADCs Comparators
Marcel Pelgrom, Pelgrom Consult, The Netherlands

The design of a comparator is often the starting point of an ADC. Comparators determine various performance parameters, like Bit-Error Rate, speed and accuracy. These aspects are analyzed and illustrated on a comparator catalog: ten published comparators will be discussed with their merits and disadvantages.

Time Interleaved ADCs
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Using time-interleaving of relatively slow analog-to-digital converters allows achieving high-speed conversion at moderate resolution. The main problem that is encountered in this type of converters is related to various forms of mismatch. Offset, gain and skew variations create various artifacts and need often calibration. After a theoretical overview, the practical aspects of time-interleaved conversion will be discussed. A number of designs are analyzed for the merits.

Limits of Nyquist ADC Architectures
Filip Tavernier, KU Leuven, Belgium

Getting the maximum speed and accuracy for the minimum power consumption is crucial in every ADC design. This multi-dimensional problem requires careful consideration of many different aspects, from the ADC architecture to the technology at hand, to achieve optimal results.
This talk starts by reviewing the recent state-of-the-art of major ADC architectures, such as flash, SAR, pipeline, and pipelined-SAR. After describing their respective operation principles, it provides a quantitative comparison of their accuracy — speed — power limits, offering insight into the architectures’ and the individual blocks’ contributions. This comparison is extended by including process effects over four deep-scaled CMOS process nodes, building unique insight into both architectural as well as technological capabilities.

Case Study of a High-Speed Single-Channel SAR ADC
Filip Tavernier, KU Leuven, Belgium

This lecture starts with an overview of speed-enhancement techniques of SAR ADCs. Next, it discusses the design and measurement of a 1.25 GS/s 7-b single-channel SAR ADC that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

Case Study of a Time-Interleaved Hybrid ADC
Filip Tavernier, KU Leuven, Belgium

ADCs with high-resolution (>10 bit), multi-GHz sample rate/bandwidth, and low power are critical components in modern communication and instrumentation systems to enable direct RF sampling. Time-interleaved (TI) RF ADCs have been extensively employed to allow these specifications. However, TI ADCs come with interleaving mismatches, namely offset, gain, timing, and bandwidth. Further, additional design overhead results from the input front-end loading, routing, clock generation/distribution, and calibration circuitry to compensate for interleaving mismatches. Hence, the interleaving factor and sub-ADC architecture become critical choices in realizing an efficient-sub-ADC and minimizing interleaving overhead to achieve optimal performance.
This talk reviews time interleaving as a popular way of extending the speed of standalone ADCs and focuses on some key aspects such as interleaving errors and interleave architectures, discussing their trade-offs. To illustrate this, the design of a state-of-the-art 8x-interleaved 5 GS/s 12 bit hybrid three-stage pipelined-SAR with analog/digital corrections is presented.

Oversampling ADCs :
Discrete-and-Continuous-time Delta-Sigma Converters
Shanthi Pavan, Indian Institute of Technology, India

Overview of oversampling and noise shaping, birds-eye view of design trade offs in delta-sigma data converters, discrete-time and continuous-time delta-sigma.

Case Study: Low-Power Data Converters (1 & 2)
Kofi Makinwa, TU Delft, Belgium

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Simulating ADCs: Frequency Domain:
FFT, Bin Choice, Windowing, Noise Level, kT/C Noise
Shanthi Pavan, Indian Institute of Technology, India

ADC simulation in the frequency domain. FFT overview, choice of input frequency, cohorent and incohorent sampling, windowing.

Continuous-Time Pipeline ADC
Shanthi Pavan, Indian Institute of Technology, India

Abstract to come.

Current Steering DAC’s
Klaas Bult, Analog Design Consult, The Netherlands

Current Steering is the architecture of choice when it comes to high speed, high performance DACs. This lecture will start completely from scratch and detail all the design aspects of current steering DACs. DAC design comes down to knowing the many different error mechanisms there are and knowing the counter measures that exist in order to get good performance, even at high frequencies.

Mismatch Shaping Multi-bit DACs
Ian Galton, UC San Diego, USA

Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

Simulating Sigma-Delta Converters
Shanthi Pavan, Indian Institute of Technology, India

Simulation of discrete- and continuous-time delta-sigma converters. The impulse-invariant transformation, the delta-sigma toolbox for MATLAB. Systematic design centering of a practical continuous-time delta-sigma converter, rapid estimation of signal and noise transfer function of a practical DSM design.

Case Study:
High-Performance Delta Sigma Converter
Shanthi Pavan, Indian Institute of Technology, India