Delta-Sigma Data Converters

On-Line Class
CET – Central European Time Zone

Week 1: July 1-5, 2024

Week 2: July 8-12, 2024

Registration deadline: June 12, 2024
Payment deadline: June 24, 2024

TEACHING HOURS
DAILY	Central European Time CET	Eastern Standard Time EST	Pacific Standard Time PST	India Standard Time IST
Module 1	4:00-5:30 pm	10:00-11:30 am	7:00-8:30 am	7:30-9:00 pm
Module 2	6:00-7:30 pm	12:00-1:30 pm	9:00-10:30 am	9:30-11:00 pm

WEEK 1: July 1-5

Monday, July 1
4:00-7:30 pm	Delta Sigma Converter Basics – Parts A & B	Shanthi Pavan
Tuesday, July2
4:00-7:30 pm	Delta Sigma Converter Basics – Parts C & D	Shanthi Pavan
Wednesday, July 3
4:00-5:30 pm	Delta Sigma Converter Basics – Part E	Shanthi Pavan
6:00-7:30 pm	High-Level Design of CT-Delta Sigma Modulators	Shanthi Pavan
Thursday, July 4
4:00-5:30 pm	Discrete-Time Delta Sigma Design	David Johns
6:00-7:30 pm	Introduction to the Delta Sigma Toolbox	David Johns
Friday, July 5
4:00-5:30 pm	Bandpass Delta Sigma ADCs	David Johns
6:00-7:30 pm	Incremental and Sensor ADCs	David Johns

WEEK 2: July 8-12, 2024

Monday, July 8
4:00-5:30 pm	Circuit Techniques to Mitigate Flicker Noise in CTDS Modulators	Shanthi Pavan
6:00-7:30 pm	Non-Idealities in Continuous-Time DS Modulators	Shanthi Pavan
Tuesday, July 9
4:00-5:30 pm	Design of Building Blocks for CTDSM Modulators – Part 1	Shanthi Pavan
6:00-7:30 pm	Design of Building Blocks for CTDSM Modulators – Part 2	Shanthi Pavan
Wednesday, July 10
4:00-5:30 pm	Systematic Design Centering of a Practical CTDSM	Shanthi Pavan
6:00-7:30 pm	FIR Feedback in CTDSMs Module 2	Shanthi Pavan
Thursday, July 11
4:00-5:30 pm	Introduction to Dynamic Element Matching and Calibration	Shanthi Pavan
6:00-7:30 pm	Cascaded Continuous-Time Delta-Sigma Converters	Shanthi Pavan
Friday, July 12
4:00-5:30 pm	Case Studies : Part 1	Shanthi Pavan
6:00-7:30 pm	Case Studies : Part 2	Shanthi Pavan

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Abstracts

Delta-Sigma Data Converters
On-Line Class, July 1-12, 2024

Delta Sigma Converter Basics, Parts A & B
Shanthi Pavan, Indian Institute of Technology

Review of quantization noise, oversampling and noise shaping. High order delta-sigma loops and Signal dependent stability.

Delta Sigma Converter Basics, Parts C, D & E
Shanthi Pavan, Indian Institute of Technology

Fundamental tradeoffs in DS modulators – maximum stable amplitude and noise shaping. Loop filter topologies for discrete-time delta-sigma converters. Simulation techniques for Delta-Sigma Modulators: windowing and spectral estimation.

High-Level Design of Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Systematic design of Continuous-Time Delta-Sigma Modulators from the DT prototype using z-transform and state space methods. The “method of moments” approach to design and intuitive understanding of Continuous-Time Delta-Sigma Modulators.

Discrete-Time Delta-Sigma Design
David Johns, University of Toronto

This talk will discuss the design of switched-capacitor delta sigma design. The basics of switched-capacitor circuits will be presented as well as circuit approaches to overcome limitations. In addition, the design of delta sigma converters using switched capacitor circuits will be discussed with the use of an example design.

Introduction to the Delta-Sigma Toolbox
David Johns, University of Toronto

This talk will give an introduction to the use of a Matlab toolbox called the ³Delta Sigma Toolbox². Extensive examples will be given as well as how to make use of state-space to use different filter topologies as well as dynamic range scaling.

Bandpass Delta-Sigma ADCs
David Johns, University of Toronto

This talk will discuss the design of Bandpass Delta Sigma ADCs which are useful in RF systems. Topics covered include resonator structures, architecture choices and example systems.

Incremental and Sensor ADCs
David Johns, University of Toronto

This talk will discuss the design of incremental ADCs as well as low-frequency sensor data converters. These goal of these converters are to not only have high linearity and SNR but also to have low offset and high accuracy.

Circuit Techniques to Mitigate Flicker Noise in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Flicker noise reduction in CTDSMs using chopping. Intuition behind the effect of chopping in CTDSMs. Circuit techniques that address chopping artifacts in CTDSMs.

Non-idealities in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Excess loop delay, and compensation techniques. Clock jitter and metastability. Clock jitter and metastability (contd). Mitigating effects of jitter in CTDSMs. Time constant variations. Loop filter nonlinearity.

Design of Building Blocks for Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Circuit techniques for the design of integrators, latches and flash ADCs, DACs – resistive, and current steering.

Systematic Design Centering a Practical Continuous-Time Delta-Sigma Modulator
Shanthi Pavan, Indian Institute of Technology

Techniques for accounting for excess delay, finite OTA gain and bandwidth and layout parasitics in a CTDSM.

FIR Deedback in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

The motivation behind FIR feedback in CTDSMs. Principle behind compensation for FIR DAC delay.

Introduction to Dynamic Element Matching and Calibration
Shanthi Pavan, Indian Institute of Technology

Analysis of element mismatch in multibit DACs. Techniques to mitigate DAC mismatch problems. Data-weighted averaging and tree-structured mismatch shaping.

Cascaded Continuous-Time Delta-Sigma Converters (Module 2)
Shanthi Pavan, Indian Institute of Technology

Motivation behind CT-MASH ADCs. CT-MASH ADC topologies. Interstage noise cancellation. Practical techniques for simulating CT-MASH converters.

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