Author Archives: Caroline

    HOTEL INFORMATION

    OPERATIONAL AMPLIFIERS: Theory & Design, November 9-13, 2020

    Prices and eventual pre-reservations have not been updated yet for 2020.

    Hotel accommodation 
    Special arrangements have been made for this course to obtain hotel reservations at reduced prices in some hotels in Delft. You must identify yourself by mentioning group code “OPAMP” when making your reservation, in order to receive the special rate. For hotel bookings received after deadline, the organizing committee will not be able to guarantee either availability of rooms or reduced prices. Also, reservations have to be made directly to a hotel, not through a booking site.

    Please make your reservation by fax or by email to one of these hotels:

    Hampshire Hotel Delft Centre
    Koepoortplaats 3
    2612 RR Delft
    Comfort single room: Euro 104.50
    Breakfast included
    Euro 2.40 city tax pp/p night
    Tel: +31 15 212-2125
    Fast booking: +31 35 677-7217
    Email: reserveringen@hoteldelftcentre.nl
    Info: http://www.hoteldelftcentre.nl
    Participants have to mention OPAMP design course during registration
    Hotel Johannes Vermeer
    Molslaan 18-22
    2611 RM Delft
    Single room: Euro 99.00
    Breakfast included
    Euro 2.40 city tax pp/p night
    Tel: +31 15 212-6466
    Fax: +31 15 213-4835
    Email: info@hotelvermeer.nl
    Info: http://www.hotelvermeer.nl
    Participants have to mention: OPAMPDeadline: October 4, 2019
    Hotel Best Western Museumhotels Delft
    Oude Delft 189
    2611 HD Delft
    20% discount on the best available rate is offered to the participants of the course.
    Tel: +31 15 215-3070
    Fax: +31 15 215-3079
    Email: info@museumhotels.nl
    Info: http://www.museumhotels.nl
    Participants have to mention OPAMP during registration to get the 20% discount
    Hotel De Plataan
    Doelenplein 10
    2611 BP Delft
    Single room is Euro 105.00
    Double room is Euro 115.00
    Upgrade to theme room is Euro 35.00 per night
    Breakfast included
    Euro 2.40 city tax pp/p night
    Tel: +31 15 212-6046
    Fax: +31 15 215-7327
    Email: info@hoteldeplataan.nl
    Info: www.hoteldeplataan.nl
    To get a 10% discount, you have to mention the reference OPAMP
    Deadline: October 4, 2019
    Hotel Juliana
    Maerten Trompstraat 33
    2628 RC Delft
    Single room: Euro 67.50
    Double room: Euro 75.00 (single use) or Euro 85.00 (double use)
    Breakfast included
    Euro 2.40 city tax pp/p night
    Tel: +31 15 256-7612
    Fax: +31 15 256-5707
    Email: info@hoteljuliana.nl
    Info: www.hoteljuliana.nl
    Participants have to mention OPAMP during registration
    Deadline: October 4, 2019

    COURSE VENUE

    LOCATION

    The course will take place at the Faculty of Electrical Engineering, Mathematics and Computer Science of Delft University of Technology, in the EWI building (the tallest building located in the University area, TU Wijk).

    Address:
    TUDelft – EEMCS
    Mekelweg 4
    2628 CD Delft
    The Netherlands.

    ACCESS TO TU DELFT 

    From Amsterdam Airport (Schiphol): by train to Delft Central Station or by car on highway A4 (Den Haag) – A13 (Delft, Rotterdam)
    From Rotterdam Central Station: by train to Delft Central Station or by car on highway A13.
    From Delft Central Station to TU Delft: by taxi or by bus (line 121).


    GENERAL INFORMATION ABOUT THE COURSE

    OPERATIONAL AMPLIFIERS: Theory & Design, November 5-9, 2018
    General information about the course

    The course is addressing systematic analysis and design as well as hands-on simulation of operational amplifiers. It is shown that the topology of all operational amplifiers can be divided in nine main overall configurations. High-frequency compensation techniques are analyzed for all nine configurations. Special focus is on low-power low-voltage architectures with rail-to-rail output and/or input ranges. The design of fully differential operational amplifiers is developed. New emphasis is on low-offset chopper amplifiers, and capacitive coupled chopper amplifiers for high input-voltage current-sense applications. During hands-on simulation hours several input, output and overall designs will be covered.

    Advanced registration

    The maximum capacity is of 40 participants, because of recent fire safety regulations. The hands-on sessions will be held in the same classroom as the regular classes. For this reason, we would like to kindly ask you to bring your own laptop (windows, Mac or Linux PCs) to the course. If for any reason you cannot bring a laptop, please let us know (in the particular comments field of the on-line registration form). Registration at reduced fee is possible by sending in the course registration until October 9, 2020. Upon receipt of the course registration form, a confirmation email will be sent together with the invoice.

    Liability

    Delft University of Technology is not liable for lost or damage to participants’ properties.

    Course organization

    The course is organized by TUDelft, EEMCS faculty, Delft, The Netherlands and by MEAD Education S.A., St-Sulpice, Switzerland

    Organizers

    Course Directors: Johan H. Huijsing, TUDelft Vlado Valence, MEAD
    Administration: Caroline Huber, MEAD
    Local Organization at TUDelft: Joyce Siemers: +31(0)15 278 5745
    Çağri Gürleyük: +31(0)15 278 6518
    OpAmps@EWI.TUDelft.NL

    HOTEL INFORMATION

    You are responsible for your hotel reservation.

    For each live course period, a number of rooms is pre-reserved for you at the Starling hotel  located just in front of the EPFL. The room is @ CHF 170.- (subject to change in 2024, will be confirmed soon) + city tax, breakfast included, and you can book at <contact@shlausanne.ch> mentioning you are coming for MEAD courses at EPFL and that we have this special rate. However, I have seen that this hotel sometimes offers larger discounts if you stay 5 nights or more. This could end to a better price. You can check here: https://starling-hotel-lausanne.com/offers/.

    If you wish to stay downtown, you can find a hotel not far from the metro M1 or M2 (you may change from a metro to the other).
    Following hotels are convenient. The list proposed is not exhaustive, but you can already choose according to your budget and availabilities. All these are at reasonable prices.

    Tulip Inn Beaulieu Lausanne
    Apartamento Lausanne
    Ibis Lausanne Centre
    Ibis styles Lausanne Center (MadHouse)
    Moxy Lausanne City
    Swiss Wine by Fassbind

    Otherwise, you can make your hotel reservation on a specialized website (ebookers, Tripadvisor or so). Hotels in Lausanne offer a bus/metro card for free, available during one’s entire stay

    Another solution that can be very advantageous is to find an Airbnb in Lausanne, there are plenty at very reasonable prices.

    We stay at your disposal for any help you may need on how to reach the hotel and/or the EPFL.


    COURSE MATERIAL

    Lecture notes will be distributed in electronic format EXCLUSIVELY. They will be made available to you on a dedicated page on this web site.

    However, in order to be able to download the course material electronically, there are two conditions:

    1. you are registered to the course and your payment has been received by the deadline mentioned here, which corresponds to the chosen course period,

    2. you sign the acceptance of our Copyright Agreement by the same deadline and send it to Caroline Huber by email to education@new.mead.ch.

    On receipt of these, the link to the notes will be given to you, at the latest one week before the course start.

    Important to note: 
    The notes provided to you electronically will NOT be delivered to you in printed form anymore, so please make your own arrangements (bring your laptop, with paper and pen or printed notes) prior to your venue to the course.


    COURSE VENUE

    The hotels in Lausanne provide a free public transportation card (bus, metro) to all their guests upon arrival. Lausanne has an excellent public transportation system, which makes it very easy to come to the EPFL.

    The courses will be held at the School of Engineering (Exact location will be indicated soon: see EPFL Plan) of the Swiss Federal Institute of Technology in Lausanne, (EPFL), Switzerland. Classroom numbers will be indicated at the information desk before the course start.

    Access to EPFL:
    Useful Links
    1. From Geneva Airport:
    a) by train to Lausanne railway station
    (Approx. 45 min.), then see 2. here below.
    b) by highway N1, way out Ecublens-EPFL
    (Approx. 30-35 min.).
    Train Time Table
    Maps and Driving Directions
    2. From Lausanne:    from the Ouchy or the railway station:
    Metro M2 up to Lausanne-Flon and then
    Metro M1 up to stop EFPL (Approx. 30 min.)
    Metro M2 Time Table
    Metro M1 Time Table
    3. From Morges railway station:
    Bus No 701 up to stop EPFL
    (Approx. 20-25 min.)
    Bus No 701 Time Table

    Walking: Once at the EPFL metro stop, follow the under-ground passage which leads to the stairs between buildings BM and BP. Climb the steps and cross the big place, straight away up to the CO buildings. Pass trough the CO buildings on your right up to buildings ELA-ELB entrance on your left. Here you are at our information desk, in front of ELA1 classroom. Classroom number will be indicated there.

    Parking: Parking on EPFL site is at your charge. You can park underground on the EPFL site (from 8:00 am to 5:00 pm, CHF 1.- the first hour, CHF 2.- for the next hours). There is also a long-lasting parking near the university (P Chamberonne) where you can park your car from 8:00 am to 5:00 pm for CHF 8.00 a day. Except for this schedule, the parking lots are free.


    GENERAL INFORMATION ABOUT THE COURSE

    Purpose: Advanced engineering courses are organized by MEAD Education throughout the year. In 2022, we are offering a part of our trainings online and another part, during the summer, on the EPFL campus. The invited lecturers are top experts in the field, currently working at leading European and American companies, research institutes and universities active in IC design. Courses will be taught in English. Each attendee will receive a certificate of attendance at the course.

    Learning objectives: These courses are aimed at providing engineers with up-to-date information on important current issues of design in analog and mixed-mode integrated circuits. In general, the content of the lectures covers introduction, state-of-the-art in the specific field and practical case studies. The intent is to give to the participants a broad coverage of hints and design methods to be applicable in practice.

    Participant Profile: The prerequisite of the course is a basic knowledge of semiconductor devices and circuits. All levels of expertise (beginners, medium and advanced engineers) can benefit of this training. Also, company managers and marketing engineers may find useful information in the trends of modern techniques and applications presented in these classes.

    Registration: If a participant selects a course but notes that some modules of another program held during the same week are of higher interest, registration to these modules is possible. On the same way, if a course lasts 4 days, it is possible to choose modules among the other programs in order to complete a 5-day formation.
    How to proceed? On the on-line regisration form, select the course you are interested in and cross the “I wish to take one or more modules of another course” field as well. The course organizer will then contact you to know exactly which modules you want to register to. Corresponding course material will be distributed as well.

    Course Location: The courses will be held at the School of Engineering (Exact rooms will be indicated soon. See EPFL Plan) of the Swiss Federal Institute of Technology in Lausanne, (EPFL), Switzerland. Classroom numbers will be indicated at the information desk before the course start.

    Course Organization:

    Administrative management: MEAD Education S.A.
    Venoge 7, 1025 St-Sulpice, Switzerland
    Organizers
    Course Directors: Prof. Maher Kayal, EPFL
    Prof. Gabor Temes, Oregon State Univ., USA
    Dr. Vlado Valence, MEAD Education
    Administration: Caroline Huber, MEAD Education
    education@mead.ch

    Power Management

    August 25-29, 2025

    Registration deadline: July 18, 2025
    Payment deadline: August 15, 2025

    Download One-Page Schedule Here

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, August 25

    8:30-10:00 am Fundamentals of SC Converters and Topologies Filip Tavernier
    10:30 am-12:00 pm Analysis and Modeling of SC Converters Filip Tavernier
    1:30-3:00 pm Power Stages Bernhard Wicht
    3:30-5:00 pm Gate Drivers Bernhard Wicht

    TUESDAY, August 26

    8:30-10:00 am GaN Drivers and Circuit Design Bernhard Wicht
    10:30 am-12:00 pm Protection and Sensing Bernhard Wicht
    1:30-3:00 pm Fundamentals of Inductive DC-DC Converters Bernhard Wicht
    3:30-5:00 pm Hybrid Converters Bernhard Wicht

    WEDNESDAY, August 27

    8:30-10:00 am Fundamentals of Linear Regulators Pavan Hanumolu
    10:30 am-12:00 pm LED Drivers Design Pavan Hanumolu
    1:30-3:00 pm Digitally Controlled DC-DC Converters Pavan Hanumolu
    3:30-5:00 pm Time-Based Control of DC-DC Converters Pavan Hanumolu

    THURSDAY, August 28

    8:30 am-12:00 pm Interference and PSRR Michiel Steyaert
    1:30-3:00 am Bandgap Voltage References Michiel Steyaert
    3:30-5:00 pm DC-DC: From Discrete Towards Fully CMOS Integrated Michiel Steyaert

    FRIDAY, August 29

    8:30-10:00 am Practical Techniques of Frequency Compensation Vadim Ivanov
    10:30 am-12:00 pm Design of LDO’s with Instant Load Regulation and Unconditional Stability Vadim Ivanov
    1:30-3:00 pm Circuit Techniques for Integrated Switching Regulators Vadim Ivanov
    3:30-5:00 pm Nanopower Design Techniques and Efficient Energy Harvesting Vadim Ivanov
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    Abstracts

    Power Management
    August 25-29, 2025
    EPFL Premises, Lausanne, Switzerland

    Fundamentals of SC Converters and Topologies
    Filip Tavernier, KU Leuven

    This lecture will discuss the working principle, fundamental characteristics, and taxonomy of switched-capacitor DC-DC converters. Three analysis techniques will be introduced that can help to understand and design SC converters: Charge Flow Analysis, Charge Balance Analysis, and Branch Analysis. These techniques will be applied to gain insight into the most commonly used SC converter topologies.

    Analysis and Modeling of SC Converters
    Filip Tavernier, KU Leuven

    This lecture will discuss the output impedance model and give an overview of the extrinsic losses of SC converters. Next, the converter topology selection and its optimization for minimal losses will be discussed, both for single-topology and multi-topology SC converters. Finally, multi-phase interleaving will be discussed as a technique to reduce switching noise.

    Power Stages
    Bernhard Wicht, Leibniz University Hanover

    After a brief overview of various power transistor types, this lecture covers power switch sizing, associated parasitics, and isolation methods. Consequently, the influence on switching behavior and losses is investigated. Fundamental circuits include switch-stacking and back-to-back configurations.

    Gate Drivers and Protection
    Bernhard Wicht, Leibniz University Hanover

    This lecture provides a detailed overview of gate driver circuits and their impact on power management system performance. The design of low-side and high-side gate drivers aims for optimizing delay, power dissipation, and area. Further topics include gate supply techniques like bootstrapping and parasitic dv/dt triggered turn-on. The lecture also covers the design of fast and robust level shifters, emphasizing resistor-based, cross-coupled, and capacitive level shifters.

    GaN Drivers and Circuit Design
    Bernhard Wicht, Leibniz University Hanover

    Gallium nitride (GaN) enables compact and efficient power electronics in various applications. With a significantly lower gate as well as output charge, GaN offers superior switching performance at frequencies in the MHz domain. This talk covers system and circuit approaches for GaN power stages and gate drivers and discusses how monolithic integration advances the overall system objectives.

    Protection and Sensing
    Bernhard Wicht, Leibniz University Hanover

    Power management designs must deal with high voltages and large currents that require protection of the connected loads and power stage from damage. They have to ensure operation within the maximum ratings. This lecture emphasizes fundamental protection functions like over-voltage, over-current, thermal protection, short circuits, and open loads. During regular operation, various conditions and quantities must be controlled and require sensing circuits, such as zero-voltage crossing detection. As an essential topic, current sensing circuits are discussed in detail.

    Fundamentals of Inductive DC-DC Converters
    Bernhard Wicht, Leibniz University Hanover

    With the increasing need for efficient power supplies, inductor-based switched-mode power supplies are widely used. They provide excellent power efficiency at the expense of increased complexity and noise. This talk introduces voltage and current mode control for inductive DC-DC converters, including control loop design and basic circuit blocks. A particular focus is on fast-switching converters with small passive components that enable a high level of integration.

    Hybrid Converters
    Bernhard Wicht, Leibniz University Hanover

    Hybrid DC-DC converters pursue a promising approach by combining capacitor-based and inductive concepts in a single converter structure. Resonant operation enables switching frequencies in the multi-megahertz range at significantly reduced dynamic losses. Better utilization of passives enables fully integrated converter designs, including passive components either on-chip or by co-integration in the same package. This lecture explores system and circuit-level solutions and presents examples, in particular, for portable applications and wearables.

    Fundamentals of Linear Regulators
    Pavan Hanumolu, University of Illinois

    Design, analysis, and practical circuit implementation of low dropout regulators (LDOs) are presented. We begin with a review of traditional LDO regulator topologies and evaluate their key performance metrics such as dropout voltage, power supply rejection ratio, load and line regulation accuracy, settling time in the presence of load step, current efficiency, and stability. Following this, we describe alternate LDO architectures and illustrate how one can tradeoff some of the performance metrics.

    LED Drivers Design
    Pavan Hanumolu, University of Illinois

    LED-based lighting is emerging as a preferred choice for both home/commercial lighting and in portable applications such as camera flash, display backlights in mobile phones, tablets, laptops. This tutorial focuses on design techniques for LED drivers geared specifically to battery-driven portable applications. Efficient DC-DC switching converter architectures to implement such LED drivers along with design examples will be presented.

    Digitally Controlled DC-DC Converters
    Pavan Hanumolu, University of Illinois

    Digital control techniques offer flexibility, reduced sensitivity to component variations, and reconfigurability of DC-DC converters compared to their analog counterparts. The circuit- and system-level tradeoffs involved in the design of digitally-controlled switching converters will be discussed. Circuit techniques to implement analog-to-digital converters and digital PWM controllers will be presented.

    Time-Based Control of DC-DC Converters
    Pavan Hanumolu, University of Illinois

    Time-based control techniques for the design of high switching frequency buck converters are presented. We first describe how to use time as the processing variable (as opposed to voltage, current, or charge) and then discuss the implementation time-based controller that operates with CMOS-level digital-like signals but without adding any quantization error. Finally, the circuit implementation details of the time-based buck converter are described.

    Interference and PSRR
    Michiel Steyaert, KU Leuven

    Some EMC interference effects in integrating RF circuits are addressed and discussed. The coupling mechanism of different building blocks to the sensitive RF circuits are addressed. Design techniques for high power supply rejection ratio in basic analog building blocks are studied.

    Bandgap Voltage References
    Michiel Steyaert, KU Leuven

    The lectures start with an introduction on merits of MOSTs versus bipolar transistors in the different positions of an operational amplifier. Then the design procedures are given for optimal op-amp design by means of the pole-zero position and Bode diagrams. A second-order Miller op-amp is discussed in great detail followed by a design procedure for third-order nested Miller op-amps. All of them are optimized towards high GBW, low noise and minimum power consumption. Finally a considerable number of other configurations are discussed and compared, among which a few very-low-voltage fully-differential operational amplifiers, involving internal common-mode feedback.

    DC-DC: From Discrete Towards Fully CMOS Integrated
    Michiel Steyaert, KU Leuven

    Trends and techniques towards fully integrated CMOS DC-DC converters is studied. Both inductive and capacitive DC-DC converters are analyzed. The different required on chip components such as inductors are discussed. Different control loop techniques are presented in order to achieve high integrated density and meanwhile achieving low ripple requirements. Many designed cases, both boost and buck are analyzed and compared with classical LDO regulators.

    Practical Techniques of Frequency Compensation
    Vadim Ivanov, Texas Instruments

    Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
    We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

    Design of the LDO’s with Instant Load Regulation and
    Unconditional Stability
    Vadim Ivanov, Texas Instruments

    Discussed is a new class of LDO’s: any load stable, with instant transient response, large power supply rejection and low noise. Examples include the embedded in SoC LDOs for the SRAM unit (5 ns reaction time on the load steps), LDO for radio transmitter (shaping the required noise vs. frequency curve) and LDO for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process.

    Circuit Techniques for Integrated Switching Regulators
    Vadim Ivanov, Texas Instruments

    Power switches: static and dynamic power loss, switch sizing, wire bonds and their inductance, parasitic vertical PNP and lateral NPN structures, substrate noise, signal grounding and isolation of the control circuitry. Switch Control: Low and high-side gate drivers, use of the bootstrap capacitors with charge regeneration, transfer of the control signal to the high-side. Low and high-side synchronous rectifiers: comparator design, minimization of delays, elimination of shoot-through currents. Feedback and frequency compensation: continuous and discontinuous operation, current and voltage mode; inductor current sensing with and without external elements; oscillator and PWM circuits; error amplifier.

    Nanopower Design Techniques and Efficient Energy Harvesting
    Vadim Ivanov, Texas Instruments

    This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.

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    Advanced Analog Circuit Design

    June 23-27, 2025

    Registration deadline: May 23, 2025
    Payment deadline: June 13, 2025

    Download one-page schedule here

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, June 23

    8:30 am-12:00 pm Time Assisted Analog Design Pavan Hanumolu
    1:30-5:00 pm Analog Builiding Blocks Kofi Makinwa

    TUESDAY, June 24

    8:30 am-12:00 pm Stability of (2-stage) Operational Amplifiers Kofi Makinwa
    1:30-3:00 pm Noise Kofi Makinwa
    3:30-5:00 pm Offset and CMRR Limitations Kofi Makinwa

    WEDNESDAY, June 25

    8:30 am-12:00 pm Offset and 1/f Noise Reduction Techniques Kofi Makinwa
    1:30-5:00 pm CMOS Switched-Capacitor Circuit Design Christian Enz

    THURSDAY, June 26

    8:30-10:00 am Practical Techniques of Frequency Compensation Vadim Ivanov
    10:30 am-12:00 pm Bandgap Voltage Reference Vadim Ivanov
    1:30-5:00 pm Techniques for OpAmp Speed and Accuracy Improvement Vadim Ivanov

    FRIDAY, June 27

    8:30-10:00 am Gain Boosting & How to Judge OpAmp Settling Behaviour Klaas Bult
    10:30 am-12:00 pm Design Mistakes You’d Rather Not Talk About Klaas Bult
    1:30-5:00 pm Continuous-Time Filters Christian Enz
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    Abstracts

    Advanced Analog Circuit Design
    August 23-27, 2025
    EPFL Premises, Lausanne, Switzerland

    Time Assisted Analog Design
    Pavan Hanumolu, University of Illinois, USA

    Time-based signal processing is emerging as a viable alternative to analog signal processing traditionally performed in voltage, current, or charge domains. This tutorial discusses time-based techniques to implement classical analog functions such as filtering, control and data conversion. Time-based circuits using voltage controlled ring oscillators will be presented and their design tradeoffs will be elucidated with the aid of circuit design examples.

    Analog Building  Blocks
    Kofi Makinwa, TU Delft, The Netherlands

    Analog integrated circuits consist of building blocks with one single or two transistors. The gain, input- and output impedance is analyzed of the three single-transistor stages i.e. the amplifier, the source follower and the cascode. The differential pairs, current source and inverter amplifiers are the most used two-transistor configurations. They are analyzed in detailed. Negative resistors are added for higher Gain and Gain-Bandwidth. Design procedures are discussed for all of them.

    Stability of Operational Amplifiers
    Kofi Makinwa, TU Delft, The Netherlands

    Two-stage operational amplifiers in unity-gain configuration, suffer from peaking unless a compensation capacitance is added, or the current is increased in the second stage. These stability conditions are examined in detail, followed by five techniques to eliminate the positive zero. One of them is feedforward, which allows a gain of over a factor of two in power efficiency. The design plans are extended to three-stage amplifiers, which offer new stabilization opportunities.

    Noise
    Kofi Makinwa, TU Delft, The Netherlands

    Abstract.

    Offset and CMRR Limitations
    Kofi Makinwa, TU Delft, The Netherlands

    Abstract.

    Offset and 1/f Noise Reduction Techniques
    Kofi Makinwa, TU Delft, The Netherlands

    The design of precision analog interfaces in CMOS is severely impaired by offset, offset drift and 1/f noise. The material covered in this module analyzes these impairments in detail and reviews the common solutions for their remedy: chopping, autozeroing, correlated double sampling and offset stabilization. We will discuss the residual nonidealities as well as pros and cons of each technique and review typical application examples. In addition, we will survey recent advances in the state-of-the-art.

    CMOS Switched-Capacitor Circuit Design
    Christian Enz, EPFL, Switzerland

    Discrete-time signals, Laplace and z-transform; Basic building blocks (opamps, switches, capacitors); Sample-and-hold circuits; SC integrators, bilinear filters and and biquads; SC amplifiers; Correlated double sampling and chopper stabilization; Nonideal effects and their correction.

    Practical Techniques of Frequency Compensation
    Vadim Ivanov, Texas Instruments, USA

    Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
    We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

    Bandgap Voltage References
    Vadim Ivanov, Texas Instruments, USA

    Discussed are error sources of the bandgap voltage references and techniques for improving their accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; single- dual and triple temperature trimming; packaging requirements; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption.

    Techniques for OpAmp Speed and Accuracy Improvement
    Vadim Ivanov, Texas Instruments, USA

    Presented is a top down design process of the OpAmps based on the structural design methodology. We will start from selection of the gain structure, followed by the implementations of gain structures as well as gradual addition of various specific functions like PSRR/CMRR improvement, slew enhancement, overload recovery. We will consider offset improvement by trimming as well as by auto-zeroing and chopping, high-and low-voltage design specifics. Most of the circuits solutions were not published before and have been used in recent industrial ICs. Yet it is not another cookbook with analog circuit recipes. The goal of this presentation is to arm the engineers with a tool helping to invent the solution for any analog design problem and, at the same time, be reasonably sure that this solution is one of the best possible for any given process and set of constraints.

    Gain Boosting & How to Judge OpAmp Settling Behaviour
    Klaas Bult, Analog Design Consult, The Netherlands

    Gain-Boosting is a means to enhance the gain of single-stage amplifiers beyond any limit, without degrading the amplifiers speed in terms of GBW or settling behaviour. This lecture discusses how to design a gain-boosting amplifier for optimal settling behaviour and also details the perfect way to judge OpAmp settling behaviour, showing any (start of) ringing (even at the lowest level) or slow settling components, applicable to any type of amplifier.

    Design Mistakes You’d Rather Not Talk About
    Klaas Bult, Analog Design Consult, The Netherlands

    Every designer makes mistakes and mistakes are not the things we are proudest of, but they are the events that we learn from most. Unfortunately, they almost never get published as only succeses are accepted in Journals and Conferences. This lecture is talking about mistakes I’ve made – and learned from a lot, the hard way.

    Continuous-Time Filters
    Christian Enz, EPFL, Switzerland

    Continuous-time filters play an important role in many communication systems and at the data conversion interface, where they are required for anti-aliasing and reconstruction. This module begins by reviewing the basic s-domain filter approximations and then looks into implementations strategies. We review active RC and gm-C topologies and study their imperfections and sensitivities to nonideal effects.

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    Cryptographic Engineering

    June 24-28, 2024

    Registration deadline: May 24, 2024
    Payment deadline: June 14, 2024

    Download One-Page Schedule Here

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, June 24

    8:30-10:00 am Introduction to Block Ciphers; DES and AES Christof Paar
    10:30-12:00 am Lightweight Block Ciphers for RFIDs Christof Paar
    1:30-3:00 pm Public-Key Cryptography Algorithms and Protocols Çetin K. Koç
    3:30-5:00 pm Integer Arithmetic Algorithms and Architectures Çetin K. Koç

    TUESDAY, June 25

    8:30-10:00 am Specialized Hardware for Secret-Key Algorithms Ingrid Verbauwhede
    10:30-12:00 am Introduction to PUFs (Physically Uncloneable Functions) Ingrid Verbauwhede
    1:30-3:00 pm Finite Field Arithmetic Algorithms and Architectures Çetin K. Koç
    3:30-5:00 pm Public-Key Cryptographic Hardware and Embedded Systems Çetin K. Koç

    WEDNESDAY, June 26

    8:30-10:00 am Introduction to Side-Channel Analysis Marc Joye
    10:30-12:00 am Block Ciphers: Attacks and Countermeasures Marc Joye
    1:30-3:00 pm Trusted Computing Architectures, SSL and IPSec Pankaj Rohatgi
    3:30-5:00 pm Electromagnetic Attacks, Countermeasures and Advanced Analysis Techniques Pankaj Rohatgi

    THURSDAY, June 27

    8:30-10:00 am RSA/ECC: Attacks and Countermeasures Marc Joye
    10:30-12:00 am Fully Homomorphic Encryption Marc Joye
    1:30-3:00 pm Post-Quantum Cryptography Algorithms Francisco Rodrìguez-Henrìquez
    3:30-5:00 pm Post-Quantum Cryptography Implementations Francisco Rodrìguez-Henrìquez

    FRIDAY, June 28

    8:30-10:00 am Random Number Generators for Cryptographic Applications Werner Schindler
    10:30-12:00 am Evaluation Criteria for Non-Deterministic Random Number Generators Werner Schindler
    1:30-3:00 pm Random Number Generator Design Constraints and Challenges Viktor Fischer
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    Abstracts

    Cryptographic Engineering
    January 24-28, 2024
    EPFL Premises, Lausanne, Switzerland

    Introduction to Block Ciphers: DES and AES
    Christof Paar, Ruhr-University Bochum, Germany

    We will first give a brief introduction to AES, DES and 3DES, which are the most widely used symmetric ciphers. We will then develop method for efficiently implementing both AES and 3DES in software. For AES, algorithms for both 32 bit CPUs and 8 bit smart card CPUs, will be treated. We will then introduce the bit-slicing method, an advanced and very efficient approach for fast software implementation of block ciphers. We will use DES as an example for illustrating bit-slicing.

    Lightweight Block Ciphers for RFIDs
    Christof Paar, Ruhr-University Bochum, Germany

    For extremely resources constrained environments such as RFIDs, sensor notes or other mobile applications, it is highly desirable to have ciphers which are extremely lightweight. We will introduce optimization techniques for low-area and low-power ciphers. PRESENT, which is an extremely compact block cipher, will be discussed as a case study.

    Public-Key Cryptography Algorithms and Protocols
    Çetin K. Koç, UC Santa Barbara, USA

    Computational requirements of RSA, Elliptic Curve Cryptography, Diffie-Hellman, ElGamal, and DSA and their ECC variants. PKC computational pyramid. PKC ALU Design. Lessons of the first RSA chip. Exponentiation and point multiplication. Addition chains. Power tree and factor method. Binary and m-ary methods. Sliding window methods. Addition-subtraction chains. Canonical encoding algorithm. The NAF algorithm and its variants. Optional: Koblitz curves and tau-adic expansions.

    Integer Arithmetic Algorithms and Architectures
    Çetin K. Koç, UC Santa Barbara, USA

    Integer rings. Addition and multiplication. Modular addition and multiplication. Montgomery multiplication and exponentiation. Multiplicative inversion. The CIOS algorithm. Arithmetic with special primes. Solinas algorithms.

    Specialized Hardware for Secret-Key Algorithms
    Ingrid Verbauwhede, KU Leuven, Belgium

    This lecture will introduce hardware implementation aspects of block ciphers and stream ciphers. The DES and AES algorithm will be discussed in detail. These ciphers are never used standalone but combined with modes of operation and integrated as IP blocks in larger systems. Very compact realizations and very high throughput realizations will also be discussed.

    Introduction to PUFs (Physically Uncloneable Functions)
    Ingrid Verbauwhede, KU Leuven, Belgium

    CMOS process variations are considered a burden to IC developers since they introduce undesirable random variability between equally designed ICs. Measuring this variability can also be profitable as a physically unclonable method of silicon device identification. This can be applied to generate strong cryptographic keys which are intrinsically bound to the embedding IC instance. In this lecture, we study and compare different proposed constructions.

    Finite Field Arithmetic Algorithms and Architectures
    Çetin K. Koç, UC Santa Barbara, USA

    Representing field elements. Polynomial and normal basis. Addition in GF(2^k). Multiplication in polynomial basis. Irreducible polynomials. Normal basis squaring. Optimal normal basis multiplication. Quadratic and sub-quadratic multiplication algorithms. Karatsuba multiplication. Recursive Karatsuba algorithm. 2-Term and 3-Term Karatsuba algorithm and generalization. Montgomery-Karatsuba formulas.

    Public-Key Cryptographic Hardware and Embedded Systems
    Çetin K. Koç, UC Santa Barbara, USA

    Scalable dual-field arithmetic. Putting together GF(p) and GF(2^k) arithmetic. Montgomery multiplication in GF(2^k). Unified or dual-field full adder. Scalable and dual-field Montgomery multiplication. PKC on embedded software. Functional characteristics of embedded platforms. Incomplete addition. Compilers and assembler optimizations. Special curve solutions.

    Introduction to Side-Channel Analysis
    Marc Joye, Zama, France

    Side-channel analysis is a powerful technique re-discovered by Kocher in 1996. The principle consists in monitoring some side-channel information like the running time, the power consumption or the electromagnetic radiation. Next, from the monitored data, the adversary tries to deduce the inner-workings of the algorithm and thereby to retrieve some secret information. This talk reviews the basics of side-channel analysis on various cryptographic algorithms. It is illustrated with practical examples and several side-channel attacks are mounted against several naive, unprotected implementations of cryptosystems.

    Block Ciphers: Attacks & Countermeasures
    Marc Joye, Zama, France

    In this lecture, we will review some attacks against implementations of block ciphers. We will also present countermeasures to prevent these attacks. Focus will be on the AES block cipher.

    Trusted Computing Architectures, SSL and IPSec
    Pankaj Rohatgi, Cryptograpy Research, USA

    Businesses, governments and individuals are increasingly reliant on complex, highly-interconnected computing platforms, mobile end-points and network centric applications to conduct much of their business. Maintaining and validating the trustworthiness of this infrastructure has therefore become critical. However, as the complexity and value of the infrastructure has increased, the number of software vulnerabilities discovered and attacks mounted against applications, platforms, end-points, identities and sensitive data within this infrastructure have grown at an even faster pace. There is a realization that given this complexity, software-only security mechanisms may not be sufficient to defend against these attacks or to evaluate the trustworthiness of a system.
    Trusted computing is an effort to use trusted hardware to assist software in improving and evaluating the security for platforms, end-points, applications, identities and data. In this lecture, I will describe the Trusted Platform Module (TPM), which provides the hardware foundations for Trusted Computing and describe several ways in which the TPM could be used as a building block to improve or validate the security of platforms, end-points, applications, data and identities.

    Electromagnetic Attacks, Countermeasures and Advanced Analysis Techniques
    Pankaj Rohatgi, Cryptograpy Research, USA

    This lecture will provide an introduction to the electromagnetic emanation (EM) side-channel. We will describe the various types of compromising EM emanations and the equipment needed to capture them. We will illustrate how compromising EM emanations can be captured from a variety of cryptographic devices and how multiple signals can be captured from each device. Next we will illustrate a variety of EM attacks on cryptographic implementations. Although the attack techniques are similar to power analysis, many EM attacks are not feasible using the power side channel, either because they exploit additional leakages present in EM channels or the power side-channel is inaccessible. Finally we will describe how one can design countermeasures against EM attacks.

    RSA/ECC:  Attacks & Countermeasures
    Marc Joye, Zama, France

    Abstract to come

    Fully Homomorphic Encryption
    Marc Joye, Zama, France

    Fully homomorphic encryption (FHE) allows computing over encrypted data. In this lecture, we will cover some advanced topics in FHE. In particular, we will cover bootstrapping of ciphertexts and its extension to programmable bootstrapping. The general case of multivariate functions over encrypted data will also be dealt with. Applications to the private evaluation of neural networks will be discussed.

    Post-Quantum Cryptography Algorithms
    Francisco Rodrìguez-Henrìquez, Cryptography Research Centre of the Technology Innovation Institute at Abu Dhabi, UAE

    As of today, most cryptographic systems deployed in the real world use asymmetric primitives that rely on the hardness of integer factorization (most notably RSA public-key encryption and signatures), or the (elliptic-curve) discrete-logarithm problem. While a sensible choice of parameters for these schemes are believed to resist attacks launched from classical computers, it is known since Shor’s seminal 1994 paper, that a large universal quantum computer will be able to solve both factoring and discrete logarithms in polynomial time. Fortunately, when sufficiently large quantum computer become a reality, this will not imply the end of efficient public-key cryptography. There exist various approaches for constructing public-key encryption or key-encapsulation mechanisms (KEMs) and signatures that — as far as we know — can resist attacks coming from large universal quantum computers.
    In this lecture we present an introduction to the most important techniques for achieving a secure and efficient implementation of so-called post-quantum cryptography, the anticipated next generation of asymmetric cryptography. Concretely, we will study five main approaches to construct such post-quantum cryptography, namely, Lattice-based Cryptography, Code-based Cryptography, Multivariate Cryptography, Hash-based Cryptography, Isogeny-based Cryptography.

    Post-Quantum Cryptography Implementation
    Francisco Rodrìguez-Henrìquez, Cryptography Research Centre of the Technology Innovation Institute at Abu Dhabi, UAE

    In this class we present an introduction to the most important techniques for achieving a secure and efficient implementation of so-called post-quantum cryptography, the anticipated next generation of asymmetric cryptography. Concretely, we will revise the algorithms and their best software implementation practices.

    Random Number Generators for Cryptographic Applications
    Werner Schindler, BSI Bund, Germany

    Many cryptographic mechanisms require random numbers, e.g. as challenges, session keys or signature parameters. Inappropriate random number generators may weaken principally strong cryptographic mechanisms considerably. Requirements are formulated that appropriate random number generators should fulfill and concrete examples are discussed. Relevant differences between deterministic and the non-deterministic random number generators are worked out.

    Evaluation Criteria for Non-Deterministic Random Number Generator
    Werner Schindler, BSI Bund, Germany

    In this lecture, I will investigate in more details the problem of physical security evaluations against side-channel attacks, with applications to implortant classes of countermeasures such as masking. In a first step, I will descibe formal approaches to quantify the information leakages and put forward their potential shortcomings. Next, I will use case studies to illustrate that one can gain good intuition about the security of certain implementation based on simple heuristic formulas.

    Random Number Generator Design Constraints and Challenges
    Viktor Fischer, Université de Saint Etienne, France

    In this lecture, we will first analyze the main characteristics of random number generators (RNGs): quality related issues such as sources of randomness, entropy extraction principles, post-processing, output bit-rate and its stability; security related issues such as existence of a mathematical model, inner testability and robustness against attacks; design related issues such as resource usage, power consumption, feasibility in logic devices and design automation. Next, we will critically analyze and compare the main existing RNG principles. Based on this analysis, we will point out pitfalls that can exist in a practical RNG design and challenges that are usually faced when designing secure RNGs according to recommendations AIS 20/AIS 31.

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