Week 1: June 9-13, 2025

Week 2: June 16-20, 2025

Registration deadline: May 26, 2025
Payment deadline: May 30, 2025

TEACHING HOURS

Monday, June 9

Tuesday, June 10

Wednesday, June 11

Delta Sigma Converter Basics – Part E

High-Level Design of CT-Delta Sigma Modulators

Thursday, June 12

Discrete-Time Delta Sigma Design

Incremental and Sensor ADCs

Friday, June 13

Monday, June 16

Tuesday, June 17

Wednesday, June 18

Thursday, June 19

Friday, June 20

Delta-Sigma Data Converters
On-Line Class, June 9-20, 2025

Delta Sigma Converter Basics, Parts A & B
Shanthi Pavan, Indian Institute of Technology

Review of quantization noise, oversampling and noise shaping. High order delta-sigma loops and  Signal dependent stability.

Delta Sigma Converter Basics, Parts C, D & E
Shanthi Pavan, Indian Institute of Technology

Fundamental tradeoffs in DS modulators – maximum stable amplitude and noise shaping. Loop filter topologies for discrete-time delta-sigma converters. Simulation techniques for Delta-Sigma Modulators: windowing and spectral estimation.

High-Level Design of Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Systematic design of Continuous-Time Delta-Sigma Modulators from the DT prototype using z-transform and state space methods. The “method of moments” approach to design and intuitive understanding of Continuous-Time Delta-Sigma Modulators.

Discrete-Time Delta-Sigma Design
David Johns, University of Toronto

This talk will discuss the design of switched-capacitor delta sigma design. The basics of switched-capacitor circuits will be presented as well as circuit approaches to overcome limitations. In addition, the design of delta sigma converters using switched capacitor circuits will be discussed with the use of an example design.

Incremental and Sensor ADCs
David Johns, University of Toronto

This talk will discuss the design of incremental ADCs as well as low-frequency sensor data converters. These goal of these converters are to not only have high linearity and SNR but also to have low offset and high accuracy.

Low-Power Opamp Design
David Johns, University of Toronto

To optimize power in opamp design, one must be familiar with a variety of issues. This lecture will cover weak/mid/strong-inversion biasing with a focus on when and where each are used in a design. Also discussed will be rapid circuit analysis techniques as well as covering design optimization for 2-stage and folded-cascode opamps.

Circuit Techniques to Mitigate Flicker Noise in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Flicker noise reduction in CTDSMs using chopping. Intuition behind the effect of chopping in CTDSMs. Circuit techniques that address chopping artifacts in CTDSMs.

Non-idealities in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Excess loop delay, and compensation techniques. Clock jitter and metastability. Clock jitter and metastability (contd). Mitigating effects of jitter in CTDSMs. Time constant variations. Loop filter nonlinearity.

Design of Building Blocks for Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Circuit techniques for the design of integrators, latches and flash ADCs, DACs – resistive, and current steering.

Systematic Design Centering a Practical Continuous-Time Delta-Sigma Modulator
Shanthi Pavan, Indian Institute of Technology

Techniques for accounting for excess delay, finite OTA gain and bandwidth and layout parasitics in a CTDSM.

FIR Deedback in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

The motivation behind FIR feedback in CTDSMs. Principle behind compensation for FIR DAC delay.

Introduction to Dynamic Element Matching and Calibration
Shanthi Pavan, Indian Institute of Technology

Analysis of element mismatch in multibit DACs. Techniques to mitigate DAC mismatch problems. Data-weighted averaging and tree-structured mismatch shaping.

Cascaded Continuous-Time Delta-Sigma Converters (Module 2)
Shanthi Pavan, Indian Institute of Technology

Motivation behind CT-MASH ADCs. CT-MASH ADC topologies. Interstage noise cancellation. Practical techniques for simulating CT-MASH converters.