Author Archives: Caroline

Week 1: September 29 – October 3, 2025

Week 2: October 6-10, 2025

Registration deadline: September 15, 2025
Payment deadline: September 19, 2025

TEACHING HOURS

Monday, September 29

Tuesday, September 30

Wednesday, October 1

Thursday, October 2

Friday, October 3

Monday, October 6

Tuesday, October 7

Wednesday, October 8

Thursday, October 9

Friday, October 10

Low-Power Analog IC Design
On-Line Class
September 29 – October 10, 2025

MOS Transistor Modeling for Low-Voltage and
Low-Power Circuit Design
Christian Enz, EPFL

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.

Design of Low-power Analog Circuits using the Inversion Coefficient
Christian Enz, EPFL

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.

Noise Performance of Elementary Circuit Blocks
Boris Murmann, University of Hawaii

Designing energy-energy efficient analog circuits requires a solid understanding of electronic noise. The material covered in these two modules requires no prerequisite knowledge and looks at shot noise (due to discreteness as charge) as an intuitive baseline for further treatment. After modeling thermal and 1/f noise at the device level, we analyze its impact on elementary circuits such as common source/gate/drain amplifiers as well as switched capacitor structures. We then expand the treatment to feedback circuits with an emphasis on sensor front ends. Lastly, we analyze noise in filters and the noise penalty paid for emulating inductors using active circuits.

Opamp Topologies and Design Fundamentals
Boris Murmann, University of Hawaii

While there exist a myriad of topologies and design tricks for integrated opamps, these two introductory modules intend to untangle the design space with an emphasis on the fundamentals. Covered topics will include: (1) Elementary building blocks operated at low supply voltage and/or low current: Current mirrors, differential pairs, inverter-based stages, low-voltage cascode configurations; (2) Basic topologies: Telescopic, folded-cascode, and multi-stage; (3) Stability and frequency compensation techniques; (4) fully differential implementation and common-mode feedback.

Low-Power High Efficiency OpAmp Design
Klaas Bult, Analog Design Consult

The goal of this lecture is to find the relationship between circuit performance and power dissipation. As an example, a commonly-used OpAmp is analysed and expressions are found that give detailed insight into what power dissipation is needed to obtain a certain performance. The result is simple expression that show power dissipation as a function of performance parameters.

Low-Power High Efficiency Residue Amplifiers
Klaas Bult, Analog Design Consult

In the past 1.5 decade, residue amplifiers have shown a remarkable 50-fold reduction in power dissipation. The findings of the previous lecture are being used to explain this reduction, through a step-by-step analysis that details which circuit techniques enabled this power reduction.

Analog Design Methodology and Practical Techniques for Frequency Compensation
Vadim Ivanov, Texas Instruments

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

nergy Efficient Voltage References, Biasing in Analog Systems and Current Sources
Vadim Ivanov, Texas Instruments

Discussed are principles of the voltage reference generation, primarily of the bandgap voltage references, its error sources and techniques for improving accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; layout and packaging; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption. Considered are biasing cores, power-on resets, design of the mirror trees and circuit techniques for current source generation with high impedance and wide voltage range.

Power Dissipation in ADC Buidling Blocks
Klaas Bult, Analog Design Consult

Choosing the correct ADC architecture is the most powerful means to obtain low power dissipation. Finding expressions for the power dissipation of all ADC building blocks, is a first step in that direction. Using the same technique described in the lecture “Low Power High Efficiency OpAmp Design”, the most common ADC building block are analysed and expressions are found for power dissipation, as a function of their performance parameters.

Power Dissipation in ADCs
Klaas Bult, Analog Design Consult

This lecture builds on the findings of the lecture “Power Dissipation in ADC Building Blocks” and uses the results found in that lecture to come to estimations of power dissipation of various kinds of ADC architectures, dependent on their performance. A comparison is made between these estimates and the results that can be found in published results.

Micropower ADCs
Kofi Makinwa, TU Delft

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Energy Efficient Sensor Interfaces
Taekwang Jang, ETHZ

Abstract.

Low-Power Frequency Reference Circuits
Taekwang Jang, ETHZ

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
In this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.

Power Management With Nanoampere Consumption and Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments

This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.

Week 1: April 15-19, 2024

Week 2: April 22-26, 2024

Registration deadline: March 27, 2024
Payment deadline: April 8, 2024

TEACHING HOURS

Monday, April 15

Tuesday, April 16

Wednesday, April 17

Thursday, April 18

Friday, April 19

Monday, April 22

Tuesday, April 23

Wednesday, April 24

Thursday, April 25

Friday, April 26

PLL Design
On-Line Class
April 15-26, 2024

Fundamentals of Analog PLLs
Michiel Steyaert, KU Leuven, Belgiu

Basic definitions and concepts of phase locked loop topologies. Frequency behaviour, stability and settling of PLL topologies. Introduction of analog, digital and fractional N synthesizers. Introduction to Phase noise and jitter.

Interference effects in PLL’s
Michiel Steyaert, KU Leuven, Belgium

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.

Spiral Inductor Interference, Deadzone and Phase Noise
Michiel Steyaert, KU Leuven, Belgium

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.

VCO Design – Jitter and Phase Noise in PLLs
Ali Hajimiri, Caltech, USA

We start this lecture with an overview of the VCO noise concepts and some of the classical work in this area. We elucidate some of the basic properties of oscillator phase noise through several thought experiments. Then we go through a step-by-step development of a time-varying noise model for oscillators and discuss the evolution of noise in an oscillator from its physical sources to frequency and amplitude fluctuations. In this process, we see how low frequency noise sources affect the oscillator behavior and discuss the impact of time-varying and correlated noise source. In the second part of the lecture, we discuss how the new design insights obtained from our model leads to novel VCO topologies that overcome some of their basic challenges and limitations. We discuss additional trade-offs in VCOs and apply them in the context of several practical design examples for a broad range of frequencies and applications. Finally, we focus our attention to the noise process in phase-locked loops and analyze it using a parallel time- and frequency-domain analysis of noise in PLLs.

Analog Fractional-N PLLs for Frequency Synthesis
Ian Galton, UC San Diego, USA

This lecture explains the extension of integer-N PLLs to fractional-N PLLs for both fine tuning resolution and in-loop VCO modulation. It presents an overview of modulus quantization noise shaping techniques, tradeoffs associated with quantization noise shaping order and PLL loop bandwidth, non-ideal effects of particular concern in fractional-N PLLs such as charge pump nonlinearities and data-dependent multi-modulus divider delays, techniques for increasing loop bandwidth, simulation techniques, and case studies of example circuits and applications.

All-Digital PLL Architecture and Implementation
Bogdan Staszewski, UCD, Ireland

The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic. This lecture presents a system level view of the ADPLL:1. Principles of phase-domain frequency synthesis 2. ADPLL closed-loop behavior 3. Direct frequency modulation of ADPLL 4. Alternative TX architectures using ADPLL and PA regulator 5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design.

Digitally-Controlled Oscillator (DCO)
Bogdan Staszewski, UCD, Ireland

A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but with a significant difference in one of the components: instead of continuously tuned varactor (variable capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed in either high or low capacitive state. The composite varactor performs digital-to-capacitance conversion. This lecture presents a circuit system level view of DCO.

Time-to-Digital Converter (TDC)
Bogdan Staszewski, UCD, Ireland

A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay (about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level implementation issues.

PLL Analysis and Modeling
Sam Palermo, Texas A&M University, USA

This talk covers modeling techniques for analog and digital PLLs. This includes linear continuous-time (s-domain) and discrete-time (z-domain) models and non-linear time-domain models that allow for optimization of system bandwidth, stability, and noise performance.

PLL Building Blocks
Sam Palermo, Texas A&M University, USA

This talk covers circuit design techniques for the main building blocks, excluding the VCO, used in analog and digital PLLs. This includes phase detectors, time-to-digital converters, analog and digital loop filters, and high-speed dividers.

Clock Generation and Distribution in Wireline Systems
Sam Palermo, Texas A&M University, USA

This talk covers clock generation and distribution schemes commonly used in wireline systems. Topics include system jitter budgeting, PLL jitter modeling, clock distribution circuitry, and multi-phase clock generation and calibration schemes.

PLL-Based Clock and Data Recovery Systems
Sam Palermo, Texas A&M University, USA

This talk covers PLL-based clock and data recovery systems for wireline communication applications. Topics include basic operation, performance metrics, CDR architectures, phase and frequency detectors, and system design considerations.

FDC-Based Digital PLLs
Ian Galton, UC San Diego, USA

While both analog and digital fractional-N PLLs introduce quantization error, the majority of digital PLLs developed to date introduce quantization error with higher power or higher spurious tones than comparable analog PLLs. Digital PLLs based on second-order delta-sigma frequency-to-digital conversion address this problem in that their quantization noise ideally is equivalent to that of analog PLLs with second-order delta-sigma modulation. This talk describes the underlying theory and practical implementation of digital PLLs based on frequency-to-digital conversion and illustrates the presented concepts with IC implementation details and measured results.

Week 1: May 11-15, 2026

Week 2: May 18-22, 2026

Registration deadline: April 27, 2026
Payment deadline: May 1, 2026

TEACHING HOURS

Monday, May 11

Tuesday, May 12

Wednesday, May 13

Thursday, May 14

Friday, May 15

Monday, May 18

Tuesday, May 19

Wednesday, May 20

Thursday, May 21

Friday, May 22

Wireline SERDES Transceivers
On-Line Class
May 11-22, 2026

Introduction to Wireline Transceivers
Pavan Hanumolu, University of Illinois, USA

An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.

Transmitters (CML/VM)
Pavan Hanumolu, University of Illinois, USA

Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.

FIR Equalizers (Tx/Rx)
Pavan Hanumolu, University of Illinois, USA

Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described

Receivers (CTLE, DFE, Adaptation)
Pavan Hanumolu, University of Illinois, USA

Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.

Phase-Locked Loops
Pavan Hanumolu, University of Illinois, USA

Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type – II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.

Clock and Data Recovery
Pavan Hanumolu, University of Illinois, USA

Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.

Phase/Frequency Detectors
Pavan Hanumolu, University of Illinois, USA

This module discusses several phase and frequency detector architectures used in modern clock and data recovery circuits. The advantages and drawback of each of the detectors will be described. Circuit implementation details will be presented.

Advanced CDRs
Pavan Hanumolu, University of Illinois, USA

This module builds on the basic CDR topology and describes architectures that can overcome fundamental jitter tolerance/transfer tradeoffs. Detailed analysis and implementation details will be presented.

Baud-Rate CDRs
Pavan Hanumolu, University of Illinois, USA

Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.

Trans-Impedance Amplifiers
Pavan Hanumolu, University of Illinois, USA

Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.

Advanced Signaling Methods
Armin Tajalli, University of Utah, USA

Moving toward data rates beyond 56 Gb/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Chordal codes, that can be used to implement very low-power and high-speed links.

Short Reach Transceiver Design Tradeoffs
Armin Tajalli, University of Utah, USA

Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.

Tradeoffs in Design of Slicers
Armin Tajalli, University of Utah, USA

Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.

Discrete-Time Front-End Design
Armin Tajalli, University of Utah, USA

Design of high-speed front-end circuits, especially for receivers, is becoming more and more challenging. The need for more complex equalization schemes highlights the importance of designing very high-speed continuous-time and discrete-time circuits. The main focus of this lecture will be on circuit topologies that modern receivers use to extend their bandwidth and functionality. The lecture will start with a short introduction on a novel design algorithm to maximize the speed and energy-efficiency of analog circuits, followed by introducing several new circuit topologies for implementing DFEs.

Optical Transmitters
Sam Palermo, Texas A&M University, USA

This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and high-performance computing systems. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.

ADC-Based RX Analysis and Digital Equalization
Sam Palermo, Texas A&M University, USA

This talk provides an overview of key concepts in ADC-based serial link receivers that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, and modeling approaches.

Wireline RX Time-Interleaved ADC Design and Calibration
Sam Palermo, Texas A&M University, USA

This talk provides an overview of the high-speed time-interleaved ADCs that are now becoming prevelant in high-performance wireline receivers. The design of high-speed sample and hold topologies, key flash and SAR ADC circuits, and advanced ADC techniques is covered. The impact of time-interleaving errors and calibration techniques are also presented.

DSP-DAC Wireline Transmitters
Sam Palermo, Texas A&M University, USA

This talk provides an overview of key concepts in DAC-based serial link transmitters that support operation over high-loss channels. Topics covered include trade-offs between analog and DAC-based transmitters, key performance metrics, high-speed current-mode and voltage-mode DAC design techniques, and DSP-based transmit equalizers.

Week 1: March 10-14, 2025

Week 2: March 17-21, 2025

Registration deadline: February 24, 2025
Payment deadline: February 28, 2025

TEACHING HOURS

Monday, March 10

Tuesday, March 11

Wednesday, March 12

Thursday, March 13

Friday, March 14

Monday, March 17

Tuesday, March 18

Wednesday, March 19

Thursday, March 20

Friday, March 21

Practical Design of Data Converters
On-Line Class
March 10-21, 2025

Basic ADC Topologies and Specifications: Overview
Marcel Pelgrom, Pelgrom Consult, The Netherlands

After an introduction in the fundamental limits given by timing and component accuracy, the basic architectures of ADCs and DACs are reviewed and the main characteristics indicated. A glossary of specification definitions is presented along with practical tips to evaluate these specifications.

ADC Comparators
Marcel Pelgrom, Pelgrom Consult, The Netherlands

The design of a comparator is often the starting point of an ADC. Comparators determine various performance parameters, like Bit-Error Rate, speed and accuracy. These aspects are analyzed and illustrated on a comparator catalog: ten published comparators will be discussed with their merits and disadvantages.

Time Interleaved ADCs
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Using time-interleaving of relatively slow analog-to-digital converters allows achieving high-speed conversion at moderate resolution. The main problem that is encountered in this type of converters is related to various forms of mismatch. Offset, gain and skew variations create various artifacts and need often calibration. After a theoretical overview, the practical aspects of time-interleaved conversion will be discussed. A number of designs are analyzed for the merits.

Limits of Nyquist ADC Architectures
Filip Tavernier, KU Leuven, Belgium

Getting the maximum speed and accuracy for the minimum power consumption is crucial in every ADC design. This multi-dimensional problem requires careful consideration of many different aspects, from the ADC architecture to the technology at hand, to achieve optimal results.
This talk starts by reviewing the recent state-of-the-art of major ADC architectures, such as flash, SAR, pipeline, and pipelined-SAR. After describing their respective operation principles, it provides a quantitative comparison of their accuracy — speed — power limits, offering insight into the architectures’ and the individual blocks’ contributions. This comparison is extended by including process effects over four deep-scaled CMOS process nodes, building unique insight into both architectural as well as technological capabilities.

Case Study of a High-Speed Single-Channel SAR ADC
Filip Tavernier, KU Leuven, Belgium

This lecture starts with an overview of speed-enhancement techniques of SAR ADCs. Next, it discusses the design and measurement of a 1.25 GS/s 7-b single-channel SAR ADC that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

Case Study of a Time-Interleaved Hybrid ADC
Filip Tavernier, KU Leuven, Belgium

ADCs with high-resolution (>10 bit), multi-GHz sample rate/bandwidth, and low power are critical components in modern communication and instrumentation systems to enable direct RF sampling. Time-interleaved (TI) RF ADCs have been extensively employed to allow these specifications. However, TI ADCs come with interleaving mismatches, namely offset, gain, timing, and bandwidth. Further, additional design overhead results from the input front-end loading, routing, clock generation/distribution, and calibration circuitry to compensate for interleaving mismatches. Hence, the interleaving factor and sub-ADC architecture become critical choices in realizing an efficient-sub-ADC and minimizing interleaving overhead to achieve optimal performance.
This talk reviews time interleaving as a popular way of extending the speed of standalone ADCs and focuses on some key aspects such as interleaving errors and interleave architectures, discussing their trade-offs. To illustrate this, the design of a state-of-the-art 8x-interleaved 5 GS/s 12 bit hybrid three-stage pipelined-SAR with analog/digital corrections is presented.

Oversampling ADCs :
Discrete-and-Continuous-time Delta-Sigma Converters
Shanthi Pavan, Indian Institute of Technology, India

Overview of oversampling and noise shaping, birds-eye view of design trade offs in delta-sigma data converters, discrete-time and continuous-time delta-sigma.

Case Study: Low-Power Data Converters (1 & 2)
Kofi Makinwa, TU Delft, Belgium

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Simulating ADCs: Frequency Domain:
FFT, Bin Choice, Windowing, Noise Level, kT/C Noise
Shanthi Pavan, Indian Institute of Technology, India

ADC simulation in the frequency domain. FFT overview, choice of input frequency, cohorent and incohorent sampling, windowing.

Continuous-Time Pipeline ADC
Shanthi Pavan, Indian Institute of Technology, India

Abstract to come.

Current Steering DAC’s
Klaas Bult, Analog Design Consult, The Netherlands

Current Steering is the architecture of choice when it comes to high speed, high performance DACs. This lecture will start completely from scratch and detail all the design aspects of current steering DACs. DAC design comes down to knowing the many different error mechanisms there are and knowing the counter measures that exist in order to get good performance, even at high frequencies.

Mismatch Shaping Multi-bit DACs
Ian Galton, UC San Diego, USA

Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

Simulating Sigma-Delta Converters
Shanthi Pavan, Indian Institute of Technology, India

Simulation of discrete- and continuous-time delta-sigma converters. The impulse-invariant transformation, the delta-sigma toolbox for MATLAB. Systematic design centering of a practical continuous-time delta-sigma converter, rapid estimation of signal and noise transfer function of a practical DSM design.

Case Study:
High-Performance Delta-Sigma Converter
Shanthi Pavan, Indian Institute of Technology, India

Week 1: January 12-16, 2025

Week 2: January 19-23, 2025

Registration deadline: January 5, 2026
Payment deadline: January 9, 2026

TEACHING HOURS

Monday, January 12

Tuesday, January 13

Wednesday, January 14

Thursday, January 15

Friday, January 16

Monday, January 19

Tuesday, January 20

Wednesday, January 21

Thursday, January 22

Friday, January 23

Techniques for Handling Noise and Variability in Analog Circuits
On-Line Class
January 12-23, 2026

Random Mismatch Origins
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Circuit design greatly depends on the ability to control and reproduce process and device parameters. Statistical variations between otherwise identical components are generally described by “mismatch” parameters.  This lecture will analyze the origins of mismatch, such as random dopant fluctuations. Understanding and mitigating these effects requires statistical means.
The general mismatch model will be discussed and compared to measurements. The application to the current variation in MOS transistors is analyzed. The relation to technological parameters, Finfet, SOI and design choices is explained.

Analyzing Mismatch and Yield in Analog Circuits
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Analog ICs with differential operation are heavily affected by mismatch. In today’s advanced technologies every circuit from SRAM cell to an I-Q mixer must deal with statistical variations.  This lecture deals with handling the statistical effects in circuits, analyzing input referred random offsets and estimating yield. Examples start with the analysis of a simple differential pair, and are extended to opamps, voltage and current steering DACs, bandgaps and other analog circuits. The theory is also applied to timing chains, ring oscillators and yield analysis of flash converters.  Options to reduce the effect of mismatch and gradients are discussed.

Layout Strategies to Reduce Offset
Marcel Pelgrom, Pelgrom Consult, The Netherlands

After an introduction on elementary IC device characteristics and circuit analysis aspects (statistics, spread, fluctuations, parametric gradients), this lecture focuses on the main attention areas of mixed-signal circuit layout, namely electrical design related issues and technology related hazards. The design part discusses topics like IR drop, power supply loops, mirroring of lay-outs,  temperature gradients and design discipline. The technology part focuses on proximity and reticle effects, advanced lithography such as double patterning, layout induced mechanical stress asymmetries, and common centroid layout solutions.  The lecture finishes with a comprehensive set of guidelines.

Fundamentals of Noise in Electronic Devices
Christian Enz, EPFL, Switzerland

After variability, noise represents the ultimate limitations of analog circuits. Designers therefore need to be able to optimize circuits for low-noise operation. This lecture starts with the presentation of the mathematical tools needed for analyzing and optimizing noise in circuits. The definition of power spectral density and its use for the calculation of noise bandwidth and noise power are given. The different types of noise, their origin and properties are described, including thermal, shot and flicker noise. The noise models of different devices are then described with a special attention to the MOS transistor. The noise at RF is also described including the concept of noise matching with the noise factor and the other noise parameters. The lecture is illustrated with many examples.

Offset and CMRR: Systematic and Random
Michiel Steyaert, KU Leuven, Belgium

Mismatch between transistors, resistors and capacitors causes severe limitations in the performance of differential circuitry. They are expressed by parameters such as offset, CMRR and PSRR. These sources of random and systematic mismatch are discussed in detail. The parameters are analyzed for differential pairs, current mirrors, operational transconductance amplifiers, etc. A number of design guidelines are put together for better matching.

Voltage and Current References
Michiel Steyaert, KU Leuven, Belgium

Precision applications require a bandgap reference, with an accurate temperature coefficient over a wide range of temperatures. It usually consists of a bipolar transistor in which a resistor develops a PTAT (proportional-to-absolute-temperature) voltage. It can also be realized with a MOST in weak inversion with appropriate temperature compensation. Mismatch between the transistor parameters leads to a high level of variability, which can only be reduced by trimming. Examples are given for both bipolar and CMOS technologies.

Noise Cancellation Techniques
Filip Tavernier, KU Leuven, Belgium

Wireless receivers all start with an LNA (Low-noise amplifier) to provide gain with very low noise and distortion. Impedance and noise matching is normally used at the input. The recent ones all provide wide-band performance, and use both noise and distortion cancellation. They yield higher FOM’s than hitherto possible. The Focus is on noise cancellation techniques, some of which are applicable to any amplifier or filter.

Noise Sampling in Switched Capacitor Filters
Filip Tavernier, KU Leuven, Belgium

Switched-capacitor filters are preferred at low frequencies because they only require switches, capacitors and operational amplifiers. The matching between the capacitors determines the accuracy of the filter frequencies. Techniques are discussed to reduce the power consumption without increasing the noise levels. Numerical examples are given of several SC filter designs followed by examples of Sigma-Delta modulators using SC filters for noise shaping.

Noise Analysis in Continuous-Time and Sampled-Data Circuits
Christian Enz, EPFL, Switzerland

Noise problems have always two aspects: the description and modeling of the physical noise sources in devices and the way this noise is propagating in the circuit to the output. Whereas the above lecture is dedicated to the noise sources, this part is focused on the understanding and modeling of the noise in circuits. It starts with the calculation of noise in continuous-time circuits. The analysis allows to identify which are the fundamental device and circuit noise parameters and how they can be optimized for low-noise. The effect of noise sampling and aliasing occurring in sampled-data circuits such as switched-capacitor (SC) circuits is then described. A simple technique for calculating noise power in SC circuits is then presented. Finally, the basic principles for reducing low frequency noise are presented: autozero and correlated-double sampling in sampled-data circuits and chopper stabilization in continuous-time circuits.

Dynamic Offset-Cancellation Techniques
Kofi Makinwa, TU Delft, The Netherlands

In amplifiers, component mismatch can easily cause offsets of several (tens of) millivolts. This can be reduced to the microvolt level by the application of dynamic techniques such as auto-zeroing and chopping. Compared to the alternatives, i.e. the use of large devices or trimming, the use of dynamic techniques has the added advantage of also reducing 1/f noise and drift, making it possible to design amplifiers that are thermal-noise limited. In this lecture, an introduction to auto-zeroing and chopping will be given, their pros and cons highlighted and recent advances in the state-of-the-art reviewed.

Dynamic Element Matching Techniques
Kofi Makinwa, TU Delft, The Netherlands

Component mismatch also limits the gain accuracy of amplifiers and the linearity of data converters. In such systems, the use of dynamic element matching (DEM) allows a trade-off to be made between speed and precision. The use of DEM allows gain accuracies of a few ppm to be realized even in standard CMOS processes, as well as data-converters whose SNDR can exceed 100dB. In this lecture, an introduction to DEM will be presented, and its application to precision amplifiers and highly linear data converters will be discussed.

Case Studies in Precision Analog Circuit Design
Kofi Makinwa, TU Delft, The Netherlands

Various combinations of dynamic error correction techniques can be employed to realize precision amplifiers with superior noise, offset, linearity and gain accuracy. For instance, chopping and auto-zeroing can be combined to reduce switching artefacts, while chopping can be combined with DEM to achieve both low-offset and high gain accuracy. In this lecture, the use of such techniques to realize state-of-the-art precision amplifiers will be illustrated with the help of a number of case studies.