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    Practical Design of Data Converters

    June 17-21, 2024

    Registration deadline: May 17, 2024
    Payment deadline: June 7, 2024

    Downloard one-page schedule here

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, June 17

    8:30 am-10:00 am Specifications Marcel Pelgrom
    10:30 am-12:00 pm ADC Comparators Marcel Pelgrom
    1:30-5:00 pm Topologies Marcel Pelgrom

    TUESDAY, June 18

    8:30 am-12:00 pm Time interleaved ADC Marcel Pelgrom
    1:30-3:00 pm Limits of Nyquist ADC Architecture Filip Tavernier
    3:30-5:00 pm Case Study of a High-Speed Single-Channel SAR ADC Filip Tavernier

    WEDNESDAY, June 19

    8:30 am-10:00 am Case Study of a Time-Interleaved Hybrid ADC Filip Tavernier
    10:30 am-12:00 pm Oversampling ADCs : Discrete-and-Continuous-time Delta-Sigma Converters Shanthi Pavan
    1:30 am-3:00 am Case Study: Low-Power Data Converters (1) Kofi Makinwa
    3:30-5:00 pm Case Study: Low-Power Data Converters (2) Kofi Makinwa

    THURSDAY, June 20

    8:30 am-10:00 am Simulating ADCs: Frequency Domain: FFT, bin choice, windowing, noise level, kT/C noise Shanthi Pavan
    10:30-12:00 pm Continuous-Time Pipeline ADC Shanthi Pavan
    1:30-5:00 pm Current Steering DAC’s Klaas Bult

    FRIDAY, June 21

    8:30 am-12:00 pm Mismatch-Shaping Multi-Bit DACs Ian Galton
    1:30-3:00 pm Simulating Sigma-Delta Converters Shanthi Pavan
    3:30-5:00 pm Case Study: High-Performance Delta Sigma Converter Shanthi Pavan
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    Abstracts

    Practical Design of Data Converters
    June 17-21, 2024

    EPFL Premises, Lausanne, Switzerland

    Basic ADC Topologies and Specifications: Overview
    Marcel Pelgrom, Pelgrom Consult, The Netherlands

    After an introduction in the fundamental limits given by timing and component accuracy, the basic architectures of ADCs and DACs are reviewed and the main characteristics indicated. A glossary of specification definitions is presented along with practical tips to evaluate these specifications.

    ADCs Comparators
    Marcel Pelgrom, Pelgrom Consult, The Netherlands

    The design of a comparator is often the starting point of an ADC. Comparators determine various performance parameters, like Bit-Error Rate, speed and accuracy. These aspects are analyzed and illustrated on a comparator catalog: ten published comparators will be discussed with their merits and disadvantages.

    Time Interleaved ADCs
    Marcel Pelgrom, Pelgrom Consult, The Netherlands

    Using time-interleaving of relatively slow analog-to-digital converters allows achieving high-speed conversion at moderate resolution. The main problem that is encountered in this type of converters is related to various forms of mismatch. Offset, gain and skew variations create various artifacts and need often calibration. After a theoretical overview, the practical aspects of time-interleaved conversion will be discussed. A number of designs are analyzed for the merits.

    Limits of Nyquist ADC Architectures
    Filip Tavernier, KU Leuven, Belgium

    Getting the maximum speed and accuracy for the minimum power consumption is crucial in every ADC design. This multi-dimensional problem requires careful consideration of many different aspects, from the ADC architecture to the technology at hand, to achieve optimal results.
    This talk starts by reviewing the recent state-of-the-art of major ADC architectures, such as flash, SAR, pipeline, and pipelined-SAR. After describing their respective operation principles, it provides a quantitative comparison of their accuracy — speed — power limits, offering insight into the architectures’ and the individual blocks’ contributions. This comparison is extended by including process effects over four deep-scaled CMOS process nodes, building unique insight into both architectural as well as technological capabilities.

    Case Study of a High-Speed Single-Channel SAR ADC
    Filip Tavernier, KU Leuven, Belgium

    This lecture starts with an overview of speed-enhancement techniques of SAR ADCs. Next, it discusses the design and measurement of a 1.25 GS/s 7-b single-channel SAR ADC that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

    Case Study of a Time-Interleaved Hybrid ADC
    Filip Tavernier, KU Leuven, Belgium

    ADCs with high-resolution (>10 bit), multi-GHz sample rate/bandwidth, and low power are critical components in modern communication and instrumentation systems to enable direct RF sampling. Time-interleaved (TI) RF ADCs have been extensively employed to allow these specifications. However, TI ADCs come with interleaving mismatches, namely offset, gain, timing, and bandwidth. Further, additional design overhead results from the input front-end loading, routing, clock generation/distribution, and calibration circuitry to compensate for interleaving mismatches. Hence, the interleaving factor and sub-ADC architecture become critical choices in realizing an efficient-sub-ADC and minimizing interleaving overhead to achieve optimal performance.
    This talk reviews time interleaving as a popular way of extending the speed of standalone ADCs and focuses on some key aspects such as interleaving errors and interleave architectures, discussing their trade-offs. To illustrate this, the design of a state-of-the-art 8x-interleaved 5 GS/s 12 bit hybrid three-stage pipelined-SAR with analog/digital corrections is presented.

    Oversampling ADCs :
    Discrete-and-Continuous-time Delta-Sigma Converters
    Shanthi Pavan, Indian Institute of Technology, India

    Overview of oversampling and noise shaping, birds-eye view of design trade offs in delta-sigma data converters, discrete-time and continuous-time delta-sigma.

    Case Study: Low-Power Data Converters (1 & 2)
    Kofi Makinwa, TU Delft, Belgium

    With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

    Simulating ADCs: Frequency Domain:
    FFT, Bin Choice, Windowing, Noise Level, kT/C Noise

    Shanthi Pavan, Indian Institute of Technology, India

    ADC simulation in the frequency domain. FFT overview, choice of input frequency, cohorent and incohorent sampling, windowing.

    Continuous-Time Pipeline ADC
    Shanthi Pavan, Indian Institute of Technology, India

    Abstract to come.

    Current Steering DAC’s
    Klaas Bult, Analog Design Consult, The Netherlands

    Current Steering is the architecture of choice when it comes to high speed, high performance DACs. This lecture will start completely from scratch and detail all the design aspects of current steering DACs. DAC design comes down to knowing the many different error mechanisms there are and knowing the counter measures that exist in order to get good performance, even at high frequencies.

    Mismatch Shaping Multi-bit DACs
    Ian Galton, UC San Diego, USA

    Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

    Simulating Sigma-Delta Converters
    Shanthi Pavan, Indian Institute of Technology, India

    Simulation of discrete- and continuous-time delta-sigma converters. The impulse-invariant transformation, the delta-sigma toolbox for MATLAB. Systematic design centering of a practical continuous-time delta-sigma converter, rapid estimation of signal and noise transfer function of a practical DSM design.

    Case Study:
    High-Performance Delta Sigma Converter
    Shanthi Pavan, Indian Institute of Technology, India

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    Introduction to Analog Design

    On-Line Class
    CET – Central European Time Zone

    Download One-Page Schedule Here

    May 19-23, 2025

    Registration deadline: May 7, 2025
    Payment deadline: May 9, 2025

    registration

    TEACHING HOURS

    DAILY Central European Time CET Eastern Standard Time EST Pacific Standard Time PST India Standard Time IST
    Module 1 3:00-4:30 pm 9:00-10:30 am 6:00-7:30 am 7:30-9:00 pm
    Module 2 5:00-6:30 pm 11:00-12:30 am 8:00-9:30 am 9:30-11:00 pm

    Modules all taught by Klaas Bult, Analog Design Consult, The Netherlands

    Monday, May 19

    The MOS Transistor – How to Make Gain, Gain-Boosting

    Tuesday, May 20

    Noise, Distortion – HW1 Gain: Explanation

    Wednesday, May 21

    Basic Sub-Circuits – HW2 Biasing: Explanation

    Thursday, May 22

    Single OpAmp Architectures – HW3 Settling: Explanation

    Friday, May 23

    Two-Stage Design – HW4 Distortion: Explanation
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    Abstracts

    Introduction to Analog Design
    On-Line Class
    May 19-23, 2025
    Modules all taught by Klaas Bult,
    Analog Design Consult, The Netherlands

    Course Overview

    This course is aimed at engineers with some background in Electrical Engineering, who wish to know more about analog CMOS design. Some familiarity with SPICE simulations and some basic knowledge about feedback theory is assumed. The course will use the ubiquitous OpAmp as a design vehicle, to give some focus on the design, starts with an explanation of the MOS transistor and ends with Folded-Cascode and 2-Stage amplifiers. It deals with all aspects of analog design, including amplifier architectures, noise, distortion, frequency behavior & stability and settling behavior.

    The OpAmp

    What is an OpAmp? How do you use an OpAmp? Explanation of the MOS transistor. Various modes of operation. Derivation of the device current. Equivalent visual model based on water. Some second order effects.

    How to make Gain?

    Introduction of the Common-Source amplifier. Detailed description of how gain comes about. DC, AC and Transient behavior. Device optimization for Settling Behavior. Main limitations of the Common-Source stage in terms of frequency behavior and Gain. Introduction of the Process-Line.

    How to make more Gain?

    Introduction of the Cascode-Stage. Effects on DC, AC and Transient behavior. Limitations of the Cascode Stage. Device Transit-Frequency Ft. Cascode Process-Line. Mobility Reduction. Velocity Saturation.

    How to make even more Gain?

    Gain-Boosting introduction. Repetitive Gain-Boosting. Effect on Process-Line. High-Frequency Behavior.

    Optimizing Setlling Behavior

    Gain-Boosting Settling Behavior. Doublets. How to Judge Settling Behavior. Optimizing Gain-Boosting Settling Behavior.

    Judging Setlling Behavior

    Why is it not straightforward to judge settling behavior? Introduction of the Settling Plot. What can we learn from the Settling Plot?

    Noise

    Introduction to Noise in Circuits. Probability. Standard Deviation. Spectrum. Basic properties. kT/C-noise. MOSFET-noise. 1/f-noise. Knee-frequency and Ft. How to calculate noise of a circuit? Noise Integration and Signal to Noise Ratio (SNR).

    Noise in Circuit Design

    Noise of Common-Source Amplifier. Noise and Layout. Noise optimization. Noise Power Excess. Noise of the Cascode Transistor.

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    Advanced RF IC Design

    June 19-23, 2023

    Registration deadline: May 19, 2023
    Payment deadline: June 9, 2023

    Downloard one-page schedule here

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, June 19

    8:30 am-12:00 am RF Fundamentals and Transceivers Behzad Razavi
    1:30-5:00 pm LNA and Mixer Design Behzad Razavi

    TUESDAY, June 20

    8:30-10:00 am Modern Direct-Conversion Receivers Behzad Razavi
    10:30 am-12:00 pm New Developments in Transceiver Design Behzad Razavi
    1:30-3:00 pm Transistor-Level Design of a 2.4-GHz/5.2-GHz WiFi Receiver Behzad Razavi
    3:30-5:00 pm Case Study of a 6-GHz Receiver for WiFi and LTE Behzad Razavi

    WEDNESDAY, June 21

    8:30 am-12:00 pm mm-Wave VCO Design Behzad Razavi
    1:30-5:00 pm mm-Wave CMOS Circuit Design Patrick Reynaert

    THURSDAY, June 22

    8:30-10:00 am mm-Wave CMOS Circuit Design Examples With Transformers Patrick Reynaert
    10:30 am-12:00 pm & 1:30-3:00 pm CMOS mm-wave PA Design Patrick Reynaert
    3:30-5:00 pm Common Design-Errors and Layout Mistakes at mm-Wave Frequencies Patrick Reynaert

    FRIDAY, June 23

    8:30 am-10:00 pm Fundamentals of Beamforming for 5G and SATCOM (I) Hua Wang
    10:30 am-12:00 pm Fundamentals of Beamforming for 5G and SATCOM (II) Hua Wang
    1:30-3:00 pm 5G mm-Wave Transmitter Array Design Examples Hua Wang
    3:30-5:00 pm 5G Digital Power Amplifiers and Transmitters Hua Wang
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    Abstracts

    Advanced RF IC Design
    June 19-23, 2023

    EPFL Premises, Lausanne, Switzerland

    RF Fundamentals and Transceivers
    Behzad Razavi, UCLA, USA

    This lecture builds the foundation necessary for the overall course. We begin with the effect of nonlinearity and noise and describe quantitative measures that represent these phenomena in RF design. Examples include distortion, compression,  desensitization, intermodulation, and noise in receiver design. Next, we turn to classic transceiver architectures and focus on those that have stood the test of time and still find wide application from WiFi and cellular to millimeter-wave radios.

    LNA and Mixer Design
    Behzad Razavi, UCLA, USA

    This lecture deals with the transistor-level design of LNA and mixers for a variety of radio standards. We begin with the performance metrics of these circuits and analyze several narrowband and broadband topologies along with their pros and cons. We also present a step-by-step procedure for the design of these building blocks and describe examples that target a certain performance.

    Modern Direct-Conversion Receivers
    Behzad Razavi, UCLA, USA

    As the most popular receiver architecture for integration, direct conversion has evolved considerably over the past two decades. A salient attribute in this evolution is the ability to provide blocker tolerance by means of current-domain processing and N-path filters. This lecture delves into such concepts and describes architectures thus created.

    New Developments in Transceiver Design
    Behzad Razavi, UCLA, USA

    As radios aim for higher performance and embrace greater complexity, designers must inevitably innovate. Recent transceivers incorporate new architecture and circuit techniques that dramatically improve the performance. We present a number of examples of the state of the art to showcase these developments. Examples include receivers with noise cancellation and transmitters with high linearity.

    Transistor-Level Design of a 2.4-GHz/5.2-GHz WiFi Receiver
    Behzad Razavi, UCLA, USA

    This lecture begins with WiFi radio specifications and shows how they translate to required circuit performance. We then design each building block and form the entire receive chain. Extensive circuit simulations are used to quantify the trade-offs governing the overall system.

    Case Study of a 6-GHz Receiver for WiFi and LTE
    Behzad Razavi, UCLA, USA

    The demand for accommodating a greater number of bands and standards in mobile devices continues to challenge RF designers. This lecture presents a CMOS receiver operating from 400 MHz to 6 GHz and meeting the exacting demands of both WiFi and LTE radios. We describe the evolution of the architecture and demonstrate methods of easing noise-linearity trade-offs and improving harmonic rejection.

    mm-Wave VCO Design
    Behzad Razavi, UCLA, USA

    The design of VCOs must deal with trade-offs among the center frequency, phase noise, power consumption, and tuning range. We introduce a number of VCO topologies, analyze their phase noise behavior, and consider several specific designs. Next, we extend these concepts to the millimeter-wave range and present a step-by-step procedure for the design of a VCO operating around 30 GHz.

    mm-Wave CMOS Circuit Design
    Patrick Reynaert, KU Leuven, Belgium

    This lecture will discuss MOS transistor behaviour and performance at mm-wave frequencies, including optimization of layout and parasitics, layout optimization to minimize parasitic interconnects, stability considerations and capacitive neutralization. Also included is a comparison between bulk CMOS, FDSOI and Finfet, a discussion on passive components, both lumped and transmission-line based, layout consideration of inductors and transformers at mm-wave frequencies, shielding and maximizing quality factors of passives.

    mm-Wave CMOS Circuit Design Examples With Transformers
    Patrick Reynaert, KU Leuven, Belgium

    Discussion on transformer-based matching techniques. Imbalance and common-mode coupling in transformer-based circuits. Design examples of mm-wave MOS circuits such as LNA, VCO, amplifiers will be discussed in greater detail.

    CMOS mm-wave PA Design
    Patrick Reynaert, KU Leuven, Belgium

    These lectures start with a system-level overview of PA specifications and how they become circuit-challenges. Based on this analysis, design trade-offs for >60GHz PA design in bulk CMOS, FDSOI and Finfet are covered. Many practical examples will be discussed, covering 65nm CMOS down to 16nm Finfet. Topics such as broadband matching, power combining and minimizing AM-PM distortion will be covered in greater detail.

    Common Design-Errors and Layout Mistakes at mm-Wave Frequencies
    Patrick Reynaert, KU Leuven, Belgium

    This lecture will cover a variety of topics, such as layout of bias and ground connections, importance of bypass capacitors and their influence on common-mode oscillations and sstability verification techniques. At the end, some unexpected measurement results are explained.

    Fundamentals of Beamforming for 5G and SATCOM (I)
    Hua Wang, ETHZ, Switzerland

    This lecture will review the basic principles of phased array beamforming and non-idealities. The basic analog/digital/hybrid beamforming architectures and advanced beamforming architectures will be introduced. Different MIMO structures will be covered as well. Next, we will focus on the array system requirements for mm-Wave 5G FR2 bands for both mobile and infrastructure applications. Several basic mm-Wave array design examples for 5G wireless communication applications will be presented.

    Fundamentals of Beamforming for 5G and SATCOM (II)
    Hua Wang, ETHZ, Switzerland

    This lecture will review the array principle with an emphasis on satellite communication (SATCOM) and radar applications. We will focus on the array system requirements for SATCOM applications, such as antenna noise temperature, G/T ratio, and array tapering, etc. Next, we will study array systems for radars, such as radar MIMOs, synthetic aperture radar, and interferometric radars. Several basic mm-Wave array design examples for SATCOM and radar applications will be presented.

    5G mm-Wave Transmitter Array Design Examples
    Hua Wang, ETHZ, Switzerland

    This lecture will cover the design considerations with a particular emphasis on transmitter arrays. The antenna active impedance and load variations due to antenna coupling will be introduced. On-chip power and impedance sensors for built-in-self-testing (BiST) will be presented. Thermal considerations and thermal modeling for mm-Wave transmitter array designs will be covered as well. We will have an in-depth study on a mm-Wave transmitter array with details.

    5G Digital Power Amplifiers and Transmitters
    Hua Wang, ETHZ, Switzerland

    This lecture will introduce digital power amplifiers and RF power DACs as well as digital transmitters. The basic operation principals and different digital power cell types will be first introduced. Linearization techniques for digital power cells will be covered. Next, from signal construction perspective, polar, quadrature, and multi-phase architectures will be presented. Then, from efficiency enhancement perspective, different types of digital transmitters, in particular digital Doherty transmitters will be studied. We will present multiple digital transmitter designs including a mm-Wave mixed-signal Doherty transmitter to radically extend the dynamic range and linearity.

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    HOTEL INFORMATION

    You are responsible for your hotel reservation.

    For each live course period, a number of rooms is pre-reserved for you at the Starling hotel  located just in front of the EPFL. The room is @ CHF 170.- + city tax, breakfast included, and you can book at <contact@shlausanne.ch> mentioning you are coming for MEAD courses at EPFL and that we have this special rate. However, it appears that this hotel sometimes offers larger discounts if you stay 5 nights or more. This could end to a better price. You can check here: https://starling-hotel-lausanne.com/offers/.

    If you wish to stay downtown, you can find a hotel not far from the metro M1 or M2 (you may change from a metro to the other).
    Following hotels are convenient. The list proposed is not exhaustive, but you can already choose according to your budget and availabilities. All these are at reasonable prices.

    Tulip Inn Beaulieu Lausanne
    Apartamento Lausanne
    Ibis Lausanne Centre
    Ibis styles Lausanne Center (MadHouse)
    Moxy Lausanne City
    Swiss Wine by Fassbind

    Otherwise, you can make your hotel reservation on a specialized website (ebookers, Tripadvisor or so).

    Please note that hotels in Lausanne distribute to their guests a card allowing free metro and bus transportation in town and direct surroundings. This card is available for one’s entire stay.

    Another solution that can be very advantageous is to find an Airbnb in Lausanne, there are plenty at very reasonable prices. Be wary, however, that RBnB and private rooms may not give the free transport card; you should check before booking. More information on course venue will be sent just before the course.

    We stay (education@mead.ch) at your disposal for any help you may need on how to reach the hotel and/or the EPFL.



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