{"id":8644,"date":"2023-10-11T13:46:59","date_gmt":"2023-10-11T13:46:59","guid":{"rendered":"https:\/\/mead.ch\/mead\/?p=8644"},"modified":"2024-06-10T16:15:51","modified_gmt":"2024-06-10T16:15:51","slug":"low-power-analog-circuit-design","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/low-power-analog-circuit-design\/","title":{"rendered":"Low-Power Analog Circuit Design"},"content":{"rendered":"

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Abstracts <\/a>General Info <\/a>Course Venue <\/a>Course Material <\/a>Hotel Info<\/a><\/p>\n<\/div>\n\n\n\n
\n

June 17-21, 2024<\/h3>\n

Registration deadline: May 17, 2024<\/strong><\/span>
\nPayment deadline: June 7, 2024<\/strong>
\n<\/span>
\nDownload One-Page Schedule Here<\/a><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Course material will be distributed only<\/u> if fees have been paid by the deadline for payment.<\/strong><\/span><\/h5>\n<\/td>\n<\/tr>\n
\n

MONDAY, June 17
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:30 am-12:00 pm<\/td>\nMOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design<\/td>\nChristian Enz<\/td>\n<\/tr>\n
1:30-5:00 pm<\/td>\nDesign of Low-Power Analog Circuits using the Inversion Coefficient<\/td>\nChristian Enz<\/td>\n<\/tr>\n
\n

TUESDAY, June 18
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:30 am-12:00 pm<\/td>\nNoise Performance of Elementary Circuit Blocks<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
1:30-5:00 pm<\/td>\nOpamp Topologies and Design Fundamentals<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

WEDNESDAY, June 19
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:30-10:00 am<\/td>\nLow-Power High Efficiency OpAmp Design<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
10:30 am-12:00 pm<\/td>\nLow-Power High Efficiency Residue Amplifiers<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
1:30-3:00 pm<\/td>\nAnalog Design Methodology and Practical Techniques for Frequency Compensation<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
3:30-5:00 pm<\/td>\nEnergy Efficient Voltage References, Biasing in Analog Systems and Current Sources<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
\n

THURSDAY, June 20
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:30-10:00 am<\/td>\nPower Dissipation in ADC Buidling Blocks<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
10:30 am-12:00 pm<\/td>\nPower Dissipation in ADCs<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
1:30-5:00 pm<\/td>\nMicropower ADCs<\/td>\nKofi Makinwa<\/td>\n<\/tr>\n
\n

FRIDAY, June 21
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:30 am-12:00 pm<\/td>\nEnergy Efficient Sensor Interfaces<\/td>\nTaekwang Jang<\/td>\n<\/tr>\n
1:30am-3:00 pm<\/td>\nLow-Power Frequency Reference Circuits<\/td>\nTaekwang Jang<\/td>\n<\/tr>\n
3:30-5:00 pm<\/td>\nPower Management With Nanoampere Consumption and Efficient Energy Harvesting<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

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<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Low-Power Analog Circuit Design
\nJune 17-21, 2024
\nEPFL Premises, Lausanne, Switzerland<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design<\/b>
\nChristian Enz, EPFL<\/b><\/p>\n

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.<\/p>\n<\/td>\n<\/tr>\n

\n

Design of Low-power Analog Circuits using the Inversion Coefficient
\nChristian Enz, EPFL<\/b><\/p>\n

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm\/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.<\/p>\n<\/td>\n<\/tr>\n

\n

Noise Performance of Elementary Circuit Blocks
\nBoris Murmann, University of Hawaii
\n<\/b><\/p>\n

Designing energy-energy efficient analog circuits requires a solid understanding of electronic noise. The material covered in these two modules requires no prerequisite knowledge and looks at shot noise (due to discreteness as charge) as an intuitive baseline for further treatment. After modeling thermal and 1\/f noise at the device level, we analyze its impact on elementary circuits such as common source\/gate\/drain amplifiers as well as switched capacitor structures. We then expand the treatment to feedback circuits with an emphasis on sensor front ends. Lastly, we analyze noise in filters and the noise penalty paid for emulating inductors using active circuits.<\/p>\n<\/td>\n<\/tr>\n

\n

Opamp Topologies and Design Fundamentals
\nBoris Murmann, University of Hawaii
\n<\/b><\/p>\n

While there exist a myriad of topologies and design tricks for integrated opamps, these two introductory modules intend to untangle the design space with an emphasis on the fundamentals. Covered topics will include: (1) Elementary building blocks operated at low supply voltage and\/or low current: Current mirrors, differential pairs, inverter-based stages, low-voltage cascode configurations; (2) Basic topologies: Telescopic, folded-cascode, and multi-stage; (3) Stability and frequency compensation techniques; (4) fully differential implementation and common-mode feedback.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power High Efficiency OpAmp Design
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

The goal of this lecture is to find the relationship between circuit performance and power dissipation. As an example, a commonly-used OpAmp is analysed and expressions are found that give detailed insight into what power dissipation is needed to obtain a certain performance. The result is simple expression that show power dissipation as a function of performance parameters.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power High Efficiency Residue Amplifiers
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

In the past 1.5 decade, residue amplifiers have shown a remarkable 50-fold reduction in power dissipation. The findings of the previous lecture are being used to explain this reduction, through a step-by-step analysis that details which circuit techniques enabled this power reduction.<\/p>\n<\/td>\n<\/tr>\n

\n

Analog Design Methodology and Practical Techniques for Frequency Compensation
\nVadim Ivanov, Texas Instruments
\n<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\n

Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources
\nVadim Ivanov, Texas Instruments
\n<\/b><\/p>\n

Discussed are principles of the voltage reference generation, primarily of the bandgap voltage references, its error sources and techniques for improving accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; layout and packaging; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption. Considered are biasing cores, power-on resets, design of the mirror trees and circuit techniques for current source generation with high impedance and wide voltage range.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Dissipation in ADC Buidling Blocks
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

Choosing the correct ADC architecture is the most powerful means to obtain low power dissipation. Finding expressions for the power dissipation of all ADC building blocks, is a first step in that direction. Using the same technique described in the lecture “Low Power High Efficiency OpAmp Design\u201d, the most common ADC building block are analysed and expressions are found for power dissipation, as a function of their performance parameters.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Dissipation in ADCs
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

This lecture builds on the findings of the lecture “Power Dissipation in ADC Building Blocks\u201d and uses the results found in that lecture to come to estimations of power dissipation of various kinds of ADC architectures, dependent on their performance. A comparison is made between these estimates and the results that can be found in published results.<\/p>\n<\/td>\n<\/tr>\n

\n

Micropower ADCs
\nKofi Makinwa, TU Delft<\/b><\/p>\n

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.<\/p>\n<\/td>\n<\/tr>\n

\n

Energy Efficient Sensor Interfaces
\nTaekwang Jang, ETHZ
\n<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power Frequency Reference Circuits
\nTaekwang Jang, ETHZ
\n<\/b><\/p>\n

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
\nIn this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Management With Nanoampere Consumption and Efficient Energy Harvesting
\nVadim Ivanov, Texas Instruments<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Abstracts General Info Course Venue Course Material Hotel Info June 17-21, 2024 Registration deadline: May 17, 2024 Payment deadline: June 7, 2024 Download One-Page Schedule Here Course material will be distributed only if fees have been paid by the deadline for payment. MONDAY, June 17 8:30 am-12:00 pm MOS Transistor Modeling for Low-Voltage and Low-Power<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[34],"tags":[],"class_list":["post-8644","post","type-post","status-publish","format-standard","hentry","category-live"],"yoast_head":"\nLow-Power Analog Circuit Design - Mead Education<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/mead.ch\/mead\/low-power-analog-circuit-design\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Low-Power Analog Circuit Design - Mead Education\" \/>\n<meta property=\"og:description\" content=\"Abstracts General Info Course Venue Course Material Hotel Info June 17-21, 2024 Registration deadline: May 17, 2024 Payment deadline: June 7, 2024 Download One-Page Schedule Here Course material will be distributed only if fees have been paid by the deadline for payment. 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