{"id":5786,"date":"2021-01-22T11:22:42","date_gmt":"2021-01-22T11:22:42","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5786"},"modified":"2025-09-16T09:35:51","modified_gmt":"2025-09-16T09:35:51","slug":"low-power-analog-ic-design-2-2","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/low-power-analog-ic-design-2-2\/","title":{"rendered":"Low-Power Analog IC Design"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nCET – Central European Time Zone<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

Week 1: September 29 – October 3, 2025<\/h4>\n

Week 2: October 6-10, 2025<\/h4>\n

Registration deadline: Extended to September 19, 2025<\/strong><\/span>
\nPayment deadline: September 19, 2025<\/strong>
\n<\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
\n

TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nCentral European Time CET<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nPacific Standard Time PST<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n3:00-4:30 pm<\/td>\n9:00-10:30 am<\/td>\n6:00-7:30 am<\/td>\n6:30-8:00 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n5:00-6:30 pm<\/td>\n11:00 am – 12:30 pm<\/td>\n8:00-9:30 am<\/td>\n8:30-10:00 pm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 1: September 29 – October 3
\n<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, September 29
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nMOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design,\u00a0 (Part I)<\/td>\nChristian Enz<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nNoise Performance of Elementary Circuits<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

Tuesday, September 30
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nMOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design, (Part II)<\/td>\nChristian Enz<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nNoise Performance of Filters, Feedback & SC Circuits<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

Wednesday, October 1
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nLow-Power Frequency Reference Circuits<\/td>\nTaekwang Jang<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nOpamp Topologies and Design: Single-Stage Circuits<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

Thursday, October 2
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nDesign of Low-Power Analog Circuits using the Inversion Coefficient (Part I)<\/td>\nChristian Enz<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nOpamp Topologies and Design: Cascoded and Two-Stage Circuits<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

Friday, October 3
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nPower Dissipation in Analog Circuits<\/td>\nKlaas Bult<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 2: October 6-10
\n<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, October 6
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nAnalog Design Methodology and Practical Techniques for Frequency Compensation<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nEnergy Efficient Voltage References, Biasing in Analog Systems and Current Sources<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
\n

Tuesday, October 7
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nPower Dissipation in ADC Buidling Blocks<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nPower Dissipation in ADCs<\/td>\nKlaas Bult<\/td>\n<\/tr>\n
\n

Wednesday, October 8
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nMicropower ADCs<\/td>\nKofi Makinwa<\/td>\n<\/tr>\n
\n

Thursday, October 9
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00 -4:30 pm<\/td>\nDesign of Low-Power Analog Circuits using the Inversion Coefficient (Part II)<\/td>\nChristian Enz<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nPower Management With Nanoampere Consumption and Efficient Energy Harvesting<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
\n

Friday, October 10<\/strong><\/span>
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nEnergy Efficient Sensor Interfaces<\/td>\nTaekwang Jang<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

\n

<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Low-Power Analog IC Design
\nOn-Line Class
\n<\/b>September 29 – October 10, 2025
\n<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

MOS Transistor Modeling for Low-Voltage and
\n<\/b>Low-Power Circuit Design<\/b>
\nChristian Enz, EPFL<\/b><\/p>\n

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.<\/p>\n<\/td>\n<\/tr>\n

\n

Design of Low-power Analog Circuits using the Inversion Coefficient
\nChristian Enz, EPFL<\/b><\/p>\n

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don\u2019t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm\/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.<\/p>\n<\/td>\n<\/tr>\n

\n

Noise Performance of Elementary Circuit Blocks
\nBoris Murmann, University of Hawaii
\n<\/b><\/p>\n

Designing energy-energy efficient analog circuits requires a solid understanding of electronic noise. The material covered in these two modules requires no prerequisite knowledge and looks at shot noise (due to discreteness as charge) as an intuitive baseline for further treatment. After modeling thermal and 1\/f noise at the device level, we analyze its impact on elementary circuits such as common source\/gate\/drain amplifiers as well as switched capacitor structures. We then expand the treatment to feedback circuits with an emphasis on sensor front ends. Lastly, we analyze noise in filters and the noise penalty paid for emulating inductors using active circuits.<\/p>\n<\/td>\n<\/tr>\n

\n

Opamp Topologies and Design Fundamentals
\nBoris Murmann, University of Hawaii
\n<\/b><\/p>\n

While there exist a myriad of topologies and design tricks for integrated opamps, these two introductory modules intend to untangle the design space with an emphasis on the fundamentals. Covered topics will include: (1) Elementary building blocks operated at low supply voltage and\/or low current: Current mirrors, differential pairs, inverter-based stages, low-voltage cascode configurations; (2) Basic topologies: Telescopic, folded-cascode, and multi-stage; (3) Stability and frequency compensation techniques; (4) fully differential implementation and common-mode feedback.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power High Efficiency OpAmp Design
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

The goal of this lecture is to find the relationship between circuit performance and power dissipation. As an example, a commonly-used OpAmp is analysed and expressions are found that give detailed insight into what power dissipation is needed to obtain a certain performance. The result is simple expression that show power dissipation as a function of performance parameters.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power High Efficiency Residue Amplifiers
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

In the past 1.5 decade, residue amplifiers have shown a remarkable 50-fold reduction in power dissipation. The findings of the previous lecture are being used to explain this reduction, through a step-by-step analysis that details which circuit techniques enabled this power reduction.<\/p>\n<\/td>\n<\/tr>\n

\n

Analog Design Methodology and Practical Techniques for Frequency Compensation
\nVadim Ivanov, Texas Instruments<\/b><\/b><\/p>\n

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
\nWe will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.<\/p>\n<\/td>\n<\/tr>\n

\n

Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources
\nVadim Ivanov, Texas Instruments
\n<\/b><\/p>\n

Discussed are principles of the voltage reference generation, primarily of the bandgap voltage references, its error sources and techniques for improving accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; layout and packaging; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption. Considered are biasing cores, power-on resets, design of the mirror trees and circuit techniques for current source generation with high impedance and wide voltage range.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Dissipation in ADC Buidling Blocks
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

Choosing the correct ADC architecture is the most powerful means to obtain low power dissipation. Finding expressions for the power dissipation of all ADC building blocks, is a first step in that direction. Using the same technique described in the lecture \u201cLow Power High Efficiency OpAmp Design\u201d, the most common ADC building block are analysed and expressions are found for power dissipation, as a function of their performance parameters.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Dissipation in ADCs
\nKlaas Bult, Analog Design Consult
\n<\/b><\/p>\n

This lecture builds on the findings of the lecture \u201cPower Dissipation in ADC Building Blocks\u201d and uses the results found in that lecture to come to estimations of power dissipation of various kinds of ADC architectures, dependent on their performance. A comparison is made between these estimates and the results that can be found in published results.<\/p>\n<\/td>\n<\/tr>\n

\n

Micropower ADCs
\nKofi Makinwa, TU Delft<\/b><\/p>\n

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.<\/p>\n<\/td>\n<\/tr>\n

\n

Energy Efficient Sensor Interfaces
\nTaekwang Jang, ETHZ
\n<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power Frequency Reference Circuits
\nTaekwang Jang, ETHZ
\n<\/b><\/p>\n

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
\nIn this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Management With Nanoampere Consumption and Efficient Energy Harvesting
\nVadim Ivanov, Texas Instruments<\/b><\/p>\n

This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC\/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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