{"id":5732,"date":"2021-01-21T12:16:05","date_gmt":"2021-01-21T12:16:05","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5732"},"modified":"2026-04-09T08:39:01","modified_gmt":"2026-04-09T08:39:01","slug":"wireline-serdes-transceivers-2","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/","title":{"rendered":"Wireline SERDES Transceivers"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nCET – Central European Time Zone<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

Week 1: May 11-15, 2026<\/h4>\n

Week 2: May 18-22, 2026<\/h4>\n

Registration deadline: April 27, 2026<\/strong><\/span>
\nPayment deadline: May 1, 2026<\/strong><\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
\n

TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nCentral European Time CET<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nPacific Standard Time PST<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n3:00-4:30 pm<\/td>\n9:00-10:30 am<\/td>\n6:00-7:30 am<\/td>\n6:30-8:00 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n5:00-6:30 pm<\/td>\n11:00 am-12:30 pm<\/td>\n8:00-9:30 am<\/td>\n8:30-10:00 pm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 1: May 11-15<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, May 11<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nIntroduction to Wireline Transceivers<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nTransmitters (CML\/VM)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Tuesday, May 12<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nFIR Equalizers (Tx\/Rx)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nCTLE<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Wednesday, May 13<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nDFE, Adaptation<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nPhase-Locked Loops<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Thursday, May 14<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nAdvanced PLLs<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nClock and Data Recovery<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Friday, May 15<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nPhase\/Frequency Detectors<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nAdvanced CDRs<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 2: May 18-22<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, May 18<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nBaud-Rate CDRs<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nTrans-Impedance Amplifiers<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Tuesday, May 19<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nAdvanced Signaling Methods<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nShort Reach Transceiver Design Tradeoffs<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
\n

Wednesday, May 20<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nTradeoffs in Design of Slicers<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nDiscrete-Time Front-End Design<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
\n

Thursday, May 21<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nOptical Transmitters<\/td>\nSam Palermo<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nADC-Based RX Analysis and Digital Equalization<\/td>\nSam Palermo<\/td>\n<\/tr>\n
\n

Friday, May 22<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nWireline RX Time-Interleaved ADC Design and Calibration<\/td>\nSam Palermo<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nDSP-DAC Wireline Transmitters<\/td>\nSam Palermo<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

\n

<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Wireline SERDES Transceivers
\nOn-Line Class
\n<\/b>May 11-22, 2026<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

Introduction to Wireline Transceivers
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.<\/p>\n<\/td>\n<\/tr>\n

\n

Transmitters (CML\/VM)
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.<\/p>\n<\/td>\n<\/tr>\n

\n

FIR Equalizers (Tx\/Rx)
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described<\/p>\n<\/td>\n<\/tr>\n

\n

Receivers (CTLE, DFE, Adaptation)
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Phase-Locked Loops
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type \u2013 II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Clock and Data Recovery
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Phase\/Frequency Detectors
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

This module discusses several phase and frequency detector architectures used in modern clock and data recovery circuits. The advantages and drawback of each of the detectors will be described. Circuit implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Advanced CDRs
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

This module builds on the basic CDR topology and describes architectures that can overcome fundamental jitter tolerance\/transfer tradeoffs. Detailed analysis and implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Baud-Rate CDRs
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Trans-Impedance Amplifiers<\/strong>
\nPavan Hanumolu, University of Illinois, USA<\/strong><\/p>\n

Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.<\/p>\n<\/td>\n<\/tr>\n

\n

Advanced Signaling Methods
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Moving toward data rates beyond 56 Gb\/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Chordal codes, that can be used to implement very low-power and high-speed links.<\/p>\n<\/td>\n<\/tr>\n

\n

Short Reach Transceiver Design Tradeoffs
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.<\/p>\n<\/td>\n<\/tr>\n

\n

Tradeoffs in Design of Slicers
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.<\/p>\n<\/td>\n<\/tr>\n

\n

Discrete-Time Front-End Design
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Design of high-speed front-end circuits, especially for receivers, is becoming more and more challenging. The need for more complex equalization schemes highlights the importance of designing very high-speed continuous-time and discrete-time circuits. The main focus of this lecture will be on circuit topologies that modern receivers use to extend their bandwidth and functionality. The lecture will start with a short introduction on a novel design algorithm to maximize the speed and energy-efficiency of analog circuits, followed by introducing several new circuit topologies for implementing DFEs.<\/p>\n<\/td>\n<\/tr>\n

\n

Optical Transmitters
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and high-performance computing systems. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.<\/p>\n<\/td>\n<\/tr>\n

\n

ADC-Based RX Analysis and Digital Equalization
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk provides an overview of key concepts in ADC-based serial link receivers that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, and modeling approaches.<\/p>\n<\/td>\n<\/tr>\n

\n

Wireline RX Time-Interleaved ADC Design and Calibration
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk provides an overview of the high-speed time-interleaved ADCs that are now becoming prevelant in high-performance wireline receivers. The design of high-speed sample and hold topologies, key flash and SAR ADC circuits, and advanced ADC techniques is covered. The impact of time-interleaving errors and calibration techniques are also presented.<\/p>\n<\/td>\n<\/tr>\n

\n

DSP-DAC Wireline Transmitters
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk provides an overview of key concepts in DAC-based serial link transmitters that support operation over high-loss channels. Topics covered include trade-offs between analog and DAC-based transmitters, key performance metrics, high-speed current-mode and voltage-mode DAC design techniques, and DSP-based transmit equalizers.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

AbstractsPractical InformationCourse Material On-Line Class CET – Central European Time Zone Download One-Page Schedule Here Week 1: May 11-15, 2026 Week 2: May 18-22, 2026 Registration deadline: April 27, 2026 Payment deadline: May 1, 2026 TEACHING HOURS DAILY Central European Time CET Eastern Standard Time EST Pacific Standard Time PST India Standard Time IST Module<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[31],"tags":[],"class_list":["post-5732","post","type-post","status-publish","format-standard","hentry","category-on-line-class"],"yoast_head":"\nWireline SERDES Transceivers - Mead Education<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Wireline SERDES Transceivers - Mead Education\" \/>\n<meta property=\"og:description\" content=\"AbstractsPractical InformationCourse Material On-Line Class CET – Central European Time Zone Download One-Page Schedule Here Week 1: May 11-15, 2026 Week 2: May 18-22, 2026 Registration deadline: April 27, 2026 Payment deadline: May 1, 2026 TEACHING HOURS DAILY Central European Time CET Eastern Standard Time EST Pacific Standard Time PST India Standard Time IST Module\" \/>\n<meta property=\"og:url\" content=\"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/\" \/>\n<meta property=\"og:site_name\" content=\"Mead Education\" \/>\n<meta property=\"article:published_time\" content=\"2021-01-21T12:16:05+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-04-09T08:39:01+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png\" \/>\n\t<meta property=\"og:image:width\" content=\"123\" \/>\n\t<meta property=\"og:image:height\" content=\"40\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/png\" \/>\n<meta name=\"author\" content=\"Caroline\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Caroline\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"7 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/\"},\"author\":{\"name\":\"Caroline\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/#\\\/schema\\\/person\\\/68f80ae70ec539ddd927d312085b2f63\"},\"headline\":\"Wireline SERDES Transceivers\",\"datePublished\":\"2021-01-21T12:16:05+00:00\",\"dateModified\":\"2026-04-09T08:39:01+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/\"},\"wordCount\":1261,\"image\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wp-content\\\/uploads\\\/2013\\\/05\\\/registration.png\",\"articleSection\":[\"On-Line Class\"],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/\",\"url\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/\",\"name\":\"Wireline SERDES Transceivers - Mead Education\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wp-content\\\/uploads\\\/2013\\\/05\\\/registration.png\",\"datePublished\":\"2021-01-21T12:16:05+00:00\",\"dateModified\":\"2026-04-09T08:39:01+00:00\",\"author\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/#\\\/schema\\\/person\\\/68f80ae70ec539ddd927d312085b2f63\"},\"breadcrumb\":{\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#primaryimage\",\"url\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wp-content\\\/uploads\\\/2013\\\/05\\\/registration.png\",\"contentUrl\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wp-content\\\/uploads\\\/2013\\\/05\\\/registration.png\",\"width\":123,\"height\":40},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/wireline-serdes-transceivers-2\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/mead.ch\\\/mead\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Wireline SERDES Transceivers\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/#website\",\"url\":\"https:\\\/\\\/mead.ch\\\/mead\\\/\",\"name\":\"Mead Education\",\"description\":\"\",\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/mead.ch\\\/mead\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/mead.ch\\\/mead\\\/#\\\/schema\\\/person\\\/68f80ae70ec539ddd927d312085b2f63\",\"name\":\"Caroline\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g\",\"url\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g\",\"contentUrl\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g\",\"caption\":\"Caroline\"},\"url\":\"https:\\\/\\\/mead.ch\\\/mead\\\/author\\\/caroline\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Wireline SERDES Transceivers - Mead Education","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/","og_locale":"en_US","og_type":"article","og_title":"Wireline SERDES Transceivers - Mead Education","og_description":"AbstractsPractical InformationCourse Material On-Line Class CET – Central European Time Zone Download One-Page Schedule Here Week 1: May 11-15, 2026 Week 2: May 18-22, 2026 Registration deadline: April 27, 2026 Payment deadline: May 1, 2026 TEACHING HOURS DAILY Central European Time CET Eastern Standard Time EST Pacific Standard Time PST India Standard Time IST Module","og_url":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/","og_site_name":"Mead Education","article_published_time":"2021-01-21T12:16:05+00:00","article_modified_time":"2026-04-09T08:39:01+00:00","og_image":[{"width":123,"height":40,"url":"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png","type":"image\/png"}],"author":"Caroline","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Caroline","Est. reading time":"7 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#article","isPartOf":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/"},"author":{"name":"Caroline","@id":"https:\/\/mead.ch\/mead\/#\/schema\/person\/68f80ae70ec539ddd927d312085b2f63"},"headline":"Wireline SERDES Transceivers","datePublished":"2021-01-21T12:16:05+00:00","dateModified":"2026-04-09T08:39:01+00:00","mainEntityOfPage":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/"},"wordCount":1261,"image":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#primaryimage"},"thumbnailUrl":"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png","articleSection":["On-Line Class"],"inLanguage":"en-US"},{"@type":"WebPage","@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/","url":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/","name":"Wireline SERDES Transceivers - Mead Education","isPartOf":{"@id":"https:\/\/mead.ch\/mead\/#website"},"primaryImageOfPage":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#primaryimage"},"image":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#primaryimage"},"thumbnailUrl":"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png","datePublished":"2021-01-21T12:16:05+00:00","dateModified":"2026-04-09T08:39:01+00:00","author":{"@id":"https:\/\/mead.ch\/mead\/#\/schema\/person\/68f80ae70ec539ddd927d312085b2f63"},"breadcrumb":{"@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#primaryimage","url":"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png","contentUrl":"https:\/\/mead.ch\/mead\/wp-content\/uploads\/2013\/05\/registration.png","width":123,"height":40},{"@type":"BreadcrumbList","@id":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-2\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/mead.ch\/mead\/"},{"@type":"ListItem","position":2,"name":"Wireline SERDES Transceivers"}]},{"@type":"WebSite","@id":"https:\/\/mead.ch\/mead\/#website","url":"https:\/\/mead.ch\/mead\/","name":"Mead Education","description":"","potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/mead.ch\/mead\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Person","@id":"https:\/\/mead.ch\/mead\/#\/schema\/person\/68f80ae70ec539ddd927d312085b2f63","name":"Caroline","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/secure.gravatar.com\/avatar\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/f522f149e06cb40cc9b2e4ff491495003929c3b56676afbdfd942e717747c828?s=96&d=blank&r=g","caption":"Caroline"},"url":"https:\/\/mead.ch\/mead\/author\/caroline\/"}]}},"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p76pb6-1us","_links":{"self":[{"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/posts\/5732","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/comments?post=5732"}],"version-history":[{"count":38,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/posts\/5732\/revisions"}],"predecessor-version":[{"id":10924,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/posts\/5732\/revisions\/10924"}],"wp:attachment":[{"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/media?parent=5732"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/categories?post=5732"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/mead.ch\/mead\/wp-json\/wp\/v2\/tags?post=5732"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}