{"id":5724,"date":"2021-01-22T10:03:09","date_gmt":"2021-01-22T10:03:09","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5724"},"modified":"2026-04-10T14:32:57","modified_gmt":"2026-04-10T14:32:57","slug":"pll-design-2","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/pll-design-2\/","title":{"rendered":"PLL Design"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nCET – Central European Time Zone<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

Week 1: April 5-9, 2027<\/h4>\n

Week 2: April 12-16, 2027<\/h4>\n

Registration deadline: March 22, 2027<\/strong><\/span>
\nPayment deadline: March 26, 2027<\/strong><\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
\n

TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nCentral European Time CET<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nPacific Standard Time PST<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n3:30-5:00 pm<\/td>\n9:30-11:30 am<\/td>\n6:30-8:00 am<\/td>\n7:00-8:30 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n5:30-7:00 pm<\/td>\n11:30 am-1:00 pm<\/td>\n8:30-10:00 am<\/td>\n9:00-10:30 pm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 1: April 5-9<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, April 5<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-5:00 pm<\/td>\nFundamentals of Analog PLLs<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
5:30-7:00 pm<\/td>\nInterference Effects in PLLs<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
\n

Tuesday, April 6<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-7:00 pm<\/td>\nSpiral Inductor Interference, Deadzone and Phase Noise<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
\n

Wednesday, April 7<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-5:00 pm<\/td>\nPLL Analysis and Modeling<\/td>\nSam Palermo<\/td>\n<\/tr>\n
5:30-7:00 pm<\/td>\nPLL Building Blocks<\/td>\nSam Palermo<\/td>\n<\/tr>\n
\n

Thursday, April 8<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-7:00 pm<\/td>\nVCO Design<\/td>\nAli Hajimiri<\/td>\n<\/tr>\n
\n

Friday, April 9<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-7:00 pm<\/td>\nJitter and Phase Noise in PLLs<\/td>\nAli Hajimiri<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 2: April 12-16<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, April 12<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-7:00 pm<\/td>\nAnalog Fractional-N PLLs for Frequency Synthesis<\/td>\nIan Galton<\/td>\n<\/tr>\n
\n

Tuesday, April 13<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-5:00 pm<\/td>\nClock Generation and Distribution in Wireline Systems<\/td>\nSam Palermo<\/td>\n<\/tr>\n
5:30-7:00 pm<\/td>\nPLL-Based Clock and Data Recovery Systems<\/td>\nSam Palermo<\/td>\n<\/tr>\n
\n

Wednesday, April 14<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-7:00 pm<\/td>\nAll-Digital PLL Architecture and Implementation<\/td>\nBogdan Staszewski<\/td>\n<\/tr>\n
\n

Thursday, April 15<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-5:00 pm<\/td>\nFDC-based Digital PLLs<\/td>\nIan Galton<\/td>\n<\/tr>\n
5:30-7:00 pm<\/td>\nDigitally-Controlled Oscillator (DCO)<\/td>\nBogdan Staszewski<\/td>\n<\/tr>\n
\n

Friday, April 16<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:30-5:00 pm<\/td>\nTime-to-Digital Converter (TDC)<\/td>\nBogdan Staszewski<\/td>\n<\/tr>\n
5:30-7:00 pm<\/td>\nUltra-Low Noise PLL-Reference Co-Design Techniques<\/td>\nTaekwang Jang<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

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<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n

\"registration\"<\/a><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

PLL Design
\nOn-Line Class
\nApril 5-16, 2027<\/b><\/b><\/p>\n<\/td>\n<\/tr>\n

\n

Fundamentals of Analog PLLs
\nMichiel Steyaert, KU Leuven, Belgium<\/b><\/b><\/p>\n

Basic definitions and concepts of phase locked loop topologies. Frequency behaviour, stability and settling of PLL topologies. Introduction of analog, digital and fractional N synthesizers. Introduction to Phase noise and jitter.<\/p>\n<\/td>\n<\/tr>\n

\n

Interference effects in PLLs
\nMichiel Steyaert, KU Leuven, Belgium
\n<\/b><\/p>\n

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.<\/p>\n<\/td>\n<\/tr>\n

\n

Spiral Inductor Interference, Deadzone and Phase Noise
\nMichiel Steyaert, KU Leuven, Belgium
\n<\/b><\/p>\n

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.<\/p>\n<\/td>\n<\/tr>\n

\n

PLL Analysis and Modeling
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk covers modeling techniques for analog and digital PLLs. This includes linear continuous-time (s-domain) and discrete-time (z-domain) models and non-linear time-domain models that allow for optimization of system bandwidth, stability, and noise performance.<\/p>\n<\/td>\n<\/tr>\n

\n

PLL Building Blocks
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk covers circuit design techniques for the main building blocks, excluding the VCO, used in analog and digital PLLs. This includes phase detectors, time-to-digital converters, analog and digital loop filters, and high-speed dividers.<\/p>\n<\/td>\n<\/tr>\n

\n

VCO Design – Jitter and Phase Noise in PLLs
\nAli Hajimiri, Caltech, USA
\n<\/b><\/p>\n

We start this lecture with an overview of the VCO noise concepts and some of the classical work in this area. We elucidate some of the basic properties of oscillator phase noise through several thought experiments. Then we go through a step-by-step development of a time-varying noise model for oscillators and discuss the evolution of noise in an oscillator from its physical sources to frequency and amplitude fluctuations. In this process, we see how low frequency noise sources affect the oscillator behavior and discuss the impact of time-varying and correlated noise source. In the second part of the lecture, we discuss how the new design insights obtained from our model leads to novel VCO topologies that overcome some of their basic challenges and limitations. We discuss additional trade-offs in VCOs and apply them in the context of several practical design examples for a broad range of frequencies and applications. Finally, we focus our attention to the noise process in phase-locked loops and analyze it using a parallel time- and frequency-domain analysis of noise in PLLs.<\/p>\n<\/td>\n<\/tr>\n

\n

Analog Fractional-N PLLs for Frequency Synthesis
\nIan Galton, UC San Diego, USA
\n<\/b><\/p>\n

This lecture explains the extension of integer-N PLLs to fractional-N PLLs for both fine tuning resolution and in-loop VCO modulation. It presents an overview of modulus quantization noise shaping techniques, tradeoffs associated with quantization noise shaping order and PLL loop bandwidth, non-ideal effects of particular concern in fractional-N PLLs such as charge pump nonlinearities and data-dependent multi-modulus divider delays, techniques for increasing loop bandwidth, simulation techniques, and case studies of example circuits and applications.<\/p>\n<\/td>\n<\/tr>\n

\n

Clock Generation and Distribution in Wireline Systems
\nSam Palermo, Texas A&M University, USA<\/b><\/p>\n

This talk covers clock generation and distribution schemes commonly used in wireline systems. Topics include system jitter budgeting, PLL jitter modeling, clock distribution circuitry, and multi-phase clock generation and calibration schemes.<\/p>\n<\/td>\n<\/tr>\n

\n

PLL-Based Clock and Data Recovery Systems
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk covers PLL-based clock and data recovery systems for wireline communication applications. Topics include basic operation, performance metrics, CDR architectures, phase and frequency detectors, and system design considerations.<\/p>\n<\/td>\n<\/tr>\n

\n

All-Digital PLL Architecture and Implementation
\nBogdan Staszewski, UCD, Ireland <\/b><\/p>\n

The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase\/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic. This lecture presents a system level view of the ADPLL:1. Principles of phase-domain frequency synthesis 2. ADPLL closed-loop behavior 3. Direct frequency modulation of ADPLL 4. Alternative TX architectures using ADPLL and PA regulator 5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design.<\/p>\n<\/td>\n<\/tr>\n

\n

FDC-Based Digital PLLs
\nIan Galton, UC San Diego, USA<\/b><\/p>\n

While both analog and digital fractional-N PLLs introduce quantization error, the majority of digital PLLs developed to date introduce quantization error with higher power or higher spurious tones than comparable analog PLLs. Digital PLLs based on second-order delta-sigma frequency-to-digital conversion address this problem in that their quantization noise ideally is equivalent to that of analog PLLs with second-order delta-sigma modulation. This talk describes the underlying theory and practical implementation of digital PLLs based on frequency-to-digital conversion and illustrates the presented concepts with IC implementation details and measured results.<\/p>\n<\/td>\n<\/tr>\n

\n

Digitally-Controlled Oscillator (DCO)
\nBogdan Staszewski, UCD, Ireland <\/b><\/p>\n

A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based on an LC-tank with a negative resistance to perpetuate the oscillation\u2014 just like the traditional VCO, but with a significant difference in one of the components: instead of continuously tuned varactor (variable capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed in either high or low capacitive state. The composite varactor performs digital-to-capacitance conversion. This lecture presents a circuit system level view of DCO.<\/p>\n<\/td>\n<\/tr>\n

\n

Time-to-Digital Converter (TDC)
\nBogdan Staszewski, UCD, Ireland <\/b><\/p>\n

A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay (about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level implementation issues.<\/p>\n<\/td>\n<\/tr>\n

\n

Ultra-Low Noise PLL-Reference Co-Design Techniques
\nTaekwang Jang, ETHZ, Switzerland <\/b><\/p>\n

The generation of high-purity clock sources is becoming more crucial in today\u2019s communication systems. With the advent of advanced communication systems such as 5G wireless radios and ultrahigh-speed wireline transceivers, the required clock jitter is now around 50 fs. To meet this stringent jitter specification with a high power efficiency, the reference (typically made with a crystal oscillator) and PLL need to be co-designed and co-optimized. \u00a0This lecture discusses the fundamentals of\u00a0the crystal oscillator, frequency multiplication techniques, and advanced PLL-XO co-design to achieve ultra-low-noise performance.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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