{"id":5435,"date":"2020-06-22T16:26:50","date_gmt":"2020-06-22T16:26:50","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5435"},"modified":"2025-12-08T10:21:59","modified_gmt":"2025-12-08T10:21:59","slug":"mixed-signal-ic-design-3","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/mixed-signal-ic-design-3\/","title":{"rendered":"Mixed-Signal IC Design"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nCET – Central European Time Zone
\n<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

Week 1: October 12-16, 2026<\/h4>\n

Week 2: October 19-23, 2024<\/h4>\n

Registration deadline: September 28, 2026<\/strong><\/span>
\nPayment deadline: October 2, 2026<\/strong><\/span>
\n<\/strong><\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 1: October 12-16, 2026
\n<\/strong><\/span><\/h3>\n\n\n\n\n\n\n
\n

TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nCentral European Time CET<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nPacific Standard Time PST<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Lecture 1<\/td>\n3:00-4:30 pm<\/td>\n9:00-10:30 am<\/td>\n6:00-7:30 am<\/td>\n6:30-8:00 pm<\/td>\n<\/tr>\n
Lecture 2<\/td>\n5:00-6:30 pm<\/td>\n11:00 am-12:30 pm<\/td>\n8:00-9:30 am<\/td>\n8:30-10:00 pm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, October 12
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nThe Analog and Digital Trade-off – The Impact of Technology Scaling<\/td>\nJan Rabaey<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nULP Mixed-Signal Design for IoT and Weareable Devices –
\nSensing and Data Acquisition<\/td>\n		Jan Rabaey<\/td>\n<\/tr>\n
\n

Tuesday, October 13
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nULP Mixed-Signal Design for IoT and Weareable Devices –
\nCommunication and Computation<\/td>\n		Jan Rabaey<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nULP Mixed-Signal Design for IoT and Weareable Devices –
\nEnergy Harvesting, Storage and Conversion<\/td>\n		Jan Rabaey<\/td>\n<\/tr>\n
\n

Wednesday, October 14
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nFuture Trends in Digital Methodolgy: Evolution in Digital CMOS Technology and its Impact on Design<\/td>\nJan Rabaey<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nFuture Trends in Digital Methodolgy: Design Methodologies for Systems-on-a-Chip<\/td>\nJan Rabaey<\/td>\n<\/tr>\n
\n

Thursday, October 15
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nModeling and Simulation, Design Methodology<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

Friday, October 16
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nTime Varying Circuits in Mixed-Signal Design<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 2: October 19-23, 2026
\n<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, October 19
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nOffset and CMRR: Random and Systematic<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nFully-Differential Amplifiers<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
\n

Tuesday, October 20
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nInterference Effects and PSRR<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nCircuit Design for EMC<\/td>\nMichiel Steyaert<\/td>\n<\/tr>\n
\n

Wednesday, October 21
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nNoise Coupling in Mixed-Mode ICs: Mechanisms, Simulation,
\nMeasurement<\/td>\n		Tim Schmerbeck<\/td>\n<\/tr>\n
\n

Thursday, October 22
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nNoise Coupling in Mixed-Mode ICs: Design Strategy\/Hardware Example<\/td>\nTim Schmerbeck<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nDesign for (ESD) Robustness in Silicon ICs<\/td>\nTim Schmerbeck<\/td>\n<\/tr>\n
\n

Friday, October 23
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nPractical Techniques of Frequency Compensation<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nPower Management in Efficient Mixed-Signal Integrated Systems<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

\n

<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Mixed-Signal IC Design
\nOn-Line Class, <\/b>October 12-23, 2026<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

Trade-off Between Analog and Digital – The Impact of Technology Scaling
\nJan Rabaey, UC Berkeley<\/b><\/p>\n

For over 5 decades, technology scaling has served to reduce the cost of electronic components and functionality. The same trend is still continuing today even do some of the traditional scaling strategies such as reducing supply voltages and thresholds are hitting bounds. However, there exists a perception that technology scaling primarily serves digital design, and that analog circuitry is better off with older technologies. In this lecture, we examine the trade-off between analog and digital in the nanometer era. A number of concrete examples will be used to illustrate the possible trade-offs.<\/p>\n<\/td>\n<\/tr>\n

\n

Ultra Low-Power Mixed Signal Design for IoT
\nand Weareable Devices
\nJan Rabaey, UC Berkeley<\/b><\/p>\n

The growing importance of wireless sensor nets, ubiquitous electronics and biomedical interfaces (just to name a few) has spurred a need for mixed-signal interfaces that use only uWatts of power and hence can operate from scavenged energy. In the digital domain, sub-threshold operation at very low supply voltages is a common approach to enable ultra-low power (ULP) realization. These techniques do not translate well to the analog, mixed-signal and RF domains, where SNR and dynamic range considerations limit the scope of the supply voltage reduction. Yet, a careful balancing of the trade-off between analog and digital circuitry also allows for ULP mixed-signal to be a reality. The following three lectures will discuss various aspects of mixed-signal design for ULP wireless sensor nodes. The discussion of basic circuit design techniques will be complemented with concrete case studies.<\/p>\n

Sensing and Data Acquisition<\/b>
\nAdvances in semiconductor techniques and MEMS have allowed sensors to substantially shrink in size and power dissipation. In fact, devices are now available to integrate multiple sensing modalities on the same die, opening the door for multi-dimensional heterogeneous data acquisition. In addition, advanced applications now require that multiple data channels (up to 1000) are acquired simultaneously. Translating all these analog inputs reliably and robustly into a digital data stream that can be used for data processing and analysis poses a formidable challenge. In this lecture various techniques for ULP data acquisition (filtering, amplification, and conversion) will be discussed. Real design examples will be used to illustrate the effectiveness of these techniques.<\/p>\n

Computation and Communication<\/b>
\nMaking sense of all the data collected from the multitude of sensors requires some advanced processing, including artifact removal, transformation, feature extraction, classification and decision-making. While it is certainly possible to perform most of these operations in the \u201ccloud\u201d, latency bounds and communication limitations (which will be discussed in some detail) often require the processing to be done locally. Ultra-low energy digital processing is hence required. In this lecture, we discuss the factors limiting energy scaling in digital processing and analyze various techniques to overcome these. Special attention will be devoted to embedded machine learning and artificial intelligence techniques.<\/p>\n

Energy Harvesting, Conversion and Storage<\/b>
\nThe ubiquity of the wireless sensor nodes require that nodes be self-sufficient from an energy perspective: they either can live on a single energy charge for their complete life cycle (e.g. smart patches), or they can harvest energy from their environment. Wireless power transmission is the most common approach to energy harvesting, but other approaches collecting energy from light or mechanical vibrations are common as well. For each of these approaches, an efficient transformation of the few amount of Joules that are available into a reliable supply voltage that can power the mixed signal and digital circuitry is of essence. This is often complicated by the fact that the energy signals are weak and need to be boosted before for instance rectification can be performed. Practical examples will help to illustrate both the challenges and the possible solutions.<\/p>\n<\/td>\n<\/tr>\n

\n

Future Trends in Digital Methodolgy
\nIan Rabaey, UC Berkeley<\/b><\/p>\n

Digital logic is an essential part of every mixed-signal system-on-a-chip solution. With continued scaling of CMOS technology and the integration of more and more functionality, it has become an ever-important part. Addressing the resulting increase in complexity, caused both by technology and functionality, requires revisiting the prevailing design methodologies. While an in-depth overview in emerging trends is hard in a two-lecture sequence, we will outline some of the major trends and techniques.<\/p>\n

Lecture 1: Evolution in digital CMOS technology and its impact on design<\/b>
\nCMOS technology has continued scaling at a pace set by Moore\u2019s law. However, the nature of that scaling has changed substantially over the past decade. The minimum length of a transistor has pretty much plateaued around 12-13 nm. What has continued increasing is the density (transistors\/mm2). This further into an increase in performance and energy efficiency, albeit at a slower pace than before. In this presentation, we will discuss these scaling trends, how they are being accomplished, and how they may extend into the future. We further elaborate on how these developments impact the way digital circuits are designed, optimized and verified.<\/p>\n

Lecture 2: Design methodologies for systems-on-a-chip<\/b>
\nDigital circuits are becoming exceedingly complex. The most advanced systems-on-a-chip combine a broad range of processors (CPU, GPU), accelerators and neural processors, dedicated memory systems, networks-on-a-chip and fast input-output interfaces. Designing integrated systems of this complexity requires an evolution in design methodology, using higher levels of abstraction and more complicated building blocks. Yet, little of this is reflected in the design flows offered by the major EDA vendors today. This lecture will elaborate on how some of the emerging ideas on how design flows could evolve, including public domain components such as RISC-V, open flows and higher abstraction levels.<\/p>\n<\/td>\n<\/tr>\n

\n

Modeling and Simulation, Design Methodology
\nPavan K. Hanumolu, University of Illinois<\/b><\/p>\n

Performing transistor-level simulations of mixed-mode circuits can be very time consuming. This makes performing design space exploration and circuit optimization very difficult and some times even infeasible. This tutorial discusses ways to model and simulate large mixed-mode circuits using commonly used commercial tools. Simulation examples of mixed-mode circuits such as phase-locked loops will be discussed.<\/p>\n<\/td>\n<\/tr>\n

\n

Time Varying Circuits in Mixed-Signal Design
\nShanthi Pavan, IIT Madras
\n<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\n

Offset and CMRR: Random and Systematic<\/b>
\nMichiel Steyaert, KU Leuven<\/b><\/p>\n

Random mismatch between the equally-designed transistors in a differential pair causes offset and reduction of both the CMRR and the PSRR. This phenomenon of random mismatch is discussed in detail. Its relevance is analyzed for differential pairs, current mirrors, etc. It is followed by a number of design guidelines for better matching.<\/p>\n<\/td>\n<\/tr>\n

\n

Fully-Differential Amplifiers
\nMichiel Steyaert, KU Leuven<\/b><\/p>\n

In mixed-mode design all circuits have to be fully differential. Therefore common-mode feedback amplifiers have to be included to ensure proper biasing and common-mode rejection. They are subject to specifications such as high frequency performance and low power consumption. All possible schematics are reviewed and compared.<\/p>\n<\/td>\n<\/tr>\n

\n

Interference Effects: CMRR\/PSRR<\/b>
\nMichiel Steyaert, KU Leuven<\/b><\/p>\n

Some EMC interference effects in integrating RF circuits are addressed and discussed. The coupling mechanism of different building blocks to the sensitive RF circuits are addressed. Design techniques for high power supply rejection ratio in basic analog building blocks are studied.<\/p>\n<\/td>\n<\/tr>\n

\n

Circuit Design for EMC
\nMichiel Steyaert, KU Leuven<\/b><\/p>\n

Introduction to EMC problems: EMI, EME, EMS, charge pumping. EMS design techniques on basic building blocks: principles, current mirror, input and output structures.<\/p>\n<\/td>\n<\/tr>\n

\n

Noise Coupling in Mixed-Mode ICs: Mechanisms\/Simulation\/Measurement
\nTim Schmerbeck, IBM<\/b><\/p>\n

Survey of practical aspects of key analog and analog\/digital interaction problems: Sources of noise. Methods of coupling. Effects of substrate referencing, power distribution, chip signal isolation\/shielding techniques, packaging, card layout and circuit topology on noise. Analysis and modeling of particular analog and mixed signal noise problems along with experimental data results: Modeling and predicting chip\/package noise prior to semi-conductor processing; Chip substrate modeling.<\/p>\n<\/td>\n<\/tr>\n

\n

Noise Coupling in Mixed-Mode ICs: Design Strategy\/Hardware Example
\nTim Schmerbeck, IBM<\/b><\/p>\n

Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.<\/p>\n<\/td>\n<\/tr>\n

\n

Design for Electrostatic Discharge (ESD) Robustness in Silicon Integrated Circuits<\/b>
\nTim Schmerbeck, IBM<\/b><\/p>\n

A general treatment of the causes and prevention of chip ESD vulnerability including the ANSI ESD models with testing & simulation methods; a comprehensive treatment of common ESD protection structures; and how to design to accommodate needed protection levels. The emphasis will be on the practical application principals for designers.<\/p>\n<\/td>\n<\/tr>\n

\n

Practical Techniques of Frequency Compensation
\nVadim Ivanov, Texas Instruments
\n<\/b><\/p>\n

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
\nWe will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.<\/p>\n<\/td>\n<\/tr>\n

\n

Power Management in Efficient Mixed-Signal Integrated Systems
\nVadim Ivanov, Texas Instruments<\/b><\/p>\n

Abstract.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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