{"id":5206,"date":"2020-04-23T15:28:28","date_gmt":"2020-04-23T15:28:28","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5206"},"modified":"2021-09-03T11:17:06","modified_gmt":"2021-09-03T11:17:06","slug":"advanced-analog-circuit-design-3","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/advanced-analog-circuit-design-3\/","title":{"rendered":"Advanced Analog Circuit Design"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nPST – California Time Zone
\n<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

July 13-16, 2020<\/h3>\n

Registration deadline: June 17, 2020<\/strong>
\n<\/span>Payment deadline: June 27, 2020<\/strong>
\n<\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n
\n

TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nPacific Standard Time PST<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nCentral European Time CET<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n9:00-10:30 am<\/td>\n12:00-1:30 pm<\/td>\n6:00-7:30 pm<\/td>\n9:30-11:00 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n11:00 am-12:30 pm<\/td>\n2:00-3:30 pm<\/td>\n8:00-9:30 pm<\/td>\n11:30 pm-1:00 am<\/td>\n<\/tr>\n
Module 3<\/td>\n2:00-3:30 pm<\/td>\n5:00-6:30 pm<\/td>\n11:00 pm-12:30 am<\/td>\n2:30-4:00 am<\/td>\n<\/tr>\n
Module 4<\/td>\n4:00-5:30 pm<\/td>\n7:00-8:30 pm<\/td>\n1:00-2:30 am<\/td>\n4:30-6:00 am<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

MONDAY, July 13 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

9:00-10:30 am<\/td>\nOpamp Stability and Optimization<\/td>\nDavid Johns<\/td>\n<\/tr>\n
11:00 am-12:30 pm
\n& 2:00-3:30 pm<\/td>\n		Low Power OpAmp Design and Biasing<\/td>\nDavid Johns<\/td>\n<\/tr>\n
4:00-5:30 pm<\/td>\nCircuit Noise Limitations<\/td>\nDavid Johns<\/td>\n<\/tr>\n
\n

TUESDAY, July 14 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

9:00 am-12:30 pm<\/td>\nContinuous-Time Filters<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
2:00-3:30 pm<\/td>\nCMOS Switched-Capacitor Circuit Design<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
4:00-5:30 pm<\/td>\nOffset and 1\/f Noise Reduction Techniques<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
\n

WEDNESDAY, July 15 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

9:00 am-12:30 pm<\/td>\nGm<\/sub>\/ID<\/sub>-based Design of Amplifier Circuits<\/td>\nBoris Murmann<\/td>\n<\/tr>\n
2:00-5:30 pm<\/td>\nTime Assisted Analog Design<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

THURSDAY, July 16 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

9:00-10:30 pm<\/td>\nPractical Techniques of Frequency Compensation<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
11:00 am-12:30 pm<\/td>\nVoltage References<\/td>\nVadim Ivanov<\/td>\n<\/tr>\n
2:00-5:30 pm<\/td>\nCircuit Techniques for OpAmp Speed and
\nAccuracy Improvements<\/td>\n		Vadim Ivanov<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

\n

<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Advanced Analog Circuit Design
\nJuly 13-16, 2020
\nOn-Line Class, PST – California Time Zone<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

Opamp Stability and Optimization
\nDavid Johns, University of Toronto<\/b><\/p>\n

This talk will discuss stability as it relates to small and larger circuits. Topics covered include loop-gain\/poles relationship, return-ratio, blackman-impedance, pole-splitting, dealing with positive zero, and nested-miller compensation.<\/p>\n<\/td>\n<\/tr>\n

\n

Low Power OpAmp Design and Biasing
\nDavid Johns, University of Toronto<\/b><\/p>\n

This talk will discuss opamp design with an emphasis on low power and biasing approaches. Topics covered include weak\/strong-inversion biasing, constant-current\/PTAT\/constant-Gm biasing, differential, two\/single-stage\/multistage opamps, common-mode feedback and negative resistors.<\/p>\n<\/td>\n<\/tr>\n

\n

Circuit Noise Limitations
\nDavid Johns, University of Toronto<\/b><\/p>\n

Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.<\/p>\n<\/td>\n<\/tr>\n

\n

Continuous-Time Filters
\nBoris Murmann, Stanford University <\/b><\/p>\n

Continuous-time filters play an important role in many communication systems and at the data conversion interface, where they are required for anti-aliasing and reconstruction. This module begins by reviewing the basic s-domain filter approximations and then looks into implementations strategies. We review active RC and gm-C topologies and study their imperfections and sensitivities to nonideal effects.<\/p>\n<\/td>\n<\/tr>\n

\n

CMOS Switched-Capacitor Circuit Design
\nBoris Murmann, Stanford University<\/b><\/p>\n

Discrete-time signals, Laplace and z-transform; Basic building blocks (opamps, switches, capacitors); Sample-and-hold circuits; SC integrators, bilinear filters and and biquads; SC amplifiers; Correlated double sampling and chopper stabilization; Nonideal effects and their correction.<\/p>\n<\/td>\n<\/tr>\n

\n

Offset and 1\/f Noise Reduction Techniques
\nBoris Murmann, Stanford University<\/b><\/p>\n

The design of precision analog interfaces in CMOS is severely impaired by offset, offset drift and 1\/f noise. The material covered in this module analyzes these impairments in detail and reviews the common solutions for their remedy: chopping, autozeroing, correlated double sampling and offset stabilization. We will discuss the residual nonidealities as well as pros and cons of each technique and review typical application examples. In addition, we will survey recent advances in the state-of-the-art.<\/p>\n<\/td>\n<\/tr>\n

\n

Gm<\/sub>\/ID<\/sub>-based Design of Amplifier Circuits
\nBoris Murmann,\u00a0Stanford University <\/b><\/p>\n

The majority of textbook material on CMOS analog circuit design is based on the square-law model. While this model remains useful for teaching, it has become too inaccurate for design in nano-scale CMOS. This module presents a systematic design methodology that bridges this gap using Spice-generated look-up tables. We interpret these data based on the transistor\u2019s inversion level, employing gm\/ID as a proxy and key parameter for design. With the inclusion of other width-independent figures of merit (gm\/Cgg, gm\/gds, etc.), this allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. Since this entire flow is driven by Spice data, we maintain close agreement between the desired specs and the circuit\u2019s simulated performance. The presented material will detail the inner workings of this approach and illustrate it using two amplifier design examples (folded cascode and two-stage OTA).<\/p>\n<\/td>\n<\/tr>\n

\n

Time Assisted Analog Design
\nPavan K. Hanumolu, University of Illinois<\/b><\/p>\n

Time-based signal processing is emerging as a viable alternative to analog signal processing traditionally performed in voltage, current, or charge domains. This tutorial discusses time-based techniques to implement classical analog functions such as filtering, control and data conversion. Time-based circuits using voltage controlled ring oscillators will be presented and their design tradeoffs will be elucidated with the aid of circuit design examples.<\/p>\n<\/td>\n<\/tr>\n

\n

Practical Techniques of Frequency Compensation
\nVadim Ivanov, Texas Instruments
\n<\/b><\/p>\n

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
\nWe will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.<\/p>\n<\/td>\n<\/tr>\n

\n

Bandgap Voltage References
\nVadim Ivanov, Texas Instruments<\/b><\/p>\n

Discussed are error sources of the bandgap voltage references and techniques for improving their accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; single- dual and triple temperature trimming; packaging requirements; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption.<\/p>\n<\/td>\n<\/tr>\n

\n

Circuit Techniques for OpAmp Speed and Accuracy Improvement
\nVadim Ivanov, Texas Instruments<\/b><\/p>\n

Presented is a top down design process of the OpAmps based on the structural design methodology. We will start from selection of the gain structure, followed by the implementations of gain structures as well as gradual addition of various specific functions like PSRR\/CMRR improvement, slew enhancement, overload recovery. We will consider offset improvement by trimming as well as by auto-zeroing and chopping, high-and low-voltage design specifics. Most of the circuits solutions were not published before and have been used in recent industrial ICs. Yet it is not another cookbook with analog circuit recipes. The goal of this presentation is to arm the engineers with a tool helping to invent the solution for any analog design problem and, at the same time, be reasonably sure that this solution is one of the best possible for any given process and set of constraints.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

AbstractsPractical InformationCourse Material On-Line Class PST – California Time Zone Download One-Page Schedule Here July 13-16, 2020 Registration deadline: June 17, 2020 Payment deadline: June 27, 2020 TEACHING HOURS DAILY Pacific Standard Time PST Eastern Standard Time EST Central European Time CET India Standard Time IST Module 1 9:00-10:30 am 12:00-1:30 pm 6:00-7:30 pm 9:30-11:00<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[31],"tags":[],"class_list":["post-5206","post","type-post","status-publish","format-standard","hentry","category-on-line-class"],"yoast_head":"\nAdvanced Analog Circuit Design - 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