{"id":5203,"date":"2020-04-23T15:29:59","date_gmt":"2020-04-23T15:29:59","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5203"},"modified":"2021-09-03T11:16:37","modified_gmt":"2021-09-03T11:16:37","slug":"wireline-serdes-transceivers-3","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/wireline-serdes-transceivers-3\/","title":{"rendered":"Wireline SERDES Transceivers"},"content":{"rendered":"

<\/a><\/p>\n

Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
\nPST – California Time Zone
\n<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
\n

July 13-17, 2020<\/h3>\n

Registration deadline: June 17, 2020<\/strong>
\n<\/span>Payment deadline: June 27, 2020<\/strong>
\n<\/span><\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n
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TEACHING HOURS
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nPacific Standard Time PST<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nCentral European Time CET<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n8:00-9:30 am<\/td>\n11:00 am-12:30 pm<\/td>\n5:00-6:30 pm<\/td>\n8:30-10:00 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n10:00-11:30 am<\/td>\n1:00-2:30 pm<\/td>\n7:00-8:30 pm<\/td>\n10:30 pm-12:00 am<\/td>\n<\/tr>\n
Module 3<\/td>\n1:00-2:30 pm<\/td>\n4:00-5:30 pm<\/td>\n10:00-11:30 pm<\/td>\n1:30-3:00 am<\/td>\n<\/tr>\n
Module 4<\/td>\n3:00-4:30 pm<\/td>\n6:00-7:30 pm<\/td>\n12:00-1:30 am<\/td>\n3:30-5:00 am<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

MONDAY, July 13 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:00-9:30 am<\/td>\nIntroduction to Wireline Transceivers<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
10:00-11:30 am<\/td>\nTransmitters (CML\/VM)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
1:00-2:30 pm<\/td>\nFIR Equalizers (Tx\/Rx)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
3:00-4:30 pm<\/td>\nReceivers (CTLE, DFE, Adaptation)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

TUESDAY, July 14 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:00-11:30 pm<\/td>\nPhase-Locked Loops<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
1:00-2:30 pm<\/td>\nAdvanced PLLs<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
3:00-4:30 pm<\/td>\nClock and Data Recovery<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

WEDNESDAY, July 15 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:00-9:30 am<\/td>\nAdvanced Signaling Methods<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
10:00-11:30 pm<\/td>\nShort Reach Transceiver Design Tradeoffs<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
1:00-2:30 pm<\/td>\nTradeoffs in Design of Slicers<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
3:00-4:30 pm<\/td>\nDiscrete Time Front-End Design<\/td>\nArmin Tajalli<\/td>\n<\/tr>\n
\n

THURSDAY, July 16 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:00-9:30 am<\/td>\nClock and Data Recovery (ct’d)<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
10:00-11:30 pm<\/td>\nBaud-Rate CDRs<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
1:00-2:30 pm<\/td>\nIntroduction to PAM4 Signaling<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
3:00-4:30 pm<\/td>\nTrans-Impedance Amplifiers<\/td>\nPavan Hanumolu<\/td>\n<\/tr>\n
\n

FRIDAY, July 17 – PST Time Zone
\n<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

8:00-9:30 am<\/td>\nOptical Transmitters<\/td>\nSam Palermo<\/td>\n<\/tr>\n
10:00-11:30 am<\/td>\nDesign of ADC-Based Serial Links<\/td>\nSam Palermo<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

\n

<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Wireline SERDES Transceivers
\nJuly 13-17, 2020
\nOn-Line Class, PST – California Time Zone<\/b><\/p>\n<\/td>\n<\/tr>\n

\n

Introduction to Wireline Transceivers
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.<\/p>\n<\/td>\n<\/tr>\n

\n

Transmitters
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.<\/p>\n<\/td>\n<\/tr>\n

\n

FIR Equalizers
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described<\/p>\n<\/td>\n<\/tr>\n

\n

Receivers
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Phase-Locked Loops
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type \u2013 II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Clock and Data Recovery
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Advanced Signaling Methods
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Moving toward data rates beyond 56 Gb\/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Chordal codes, that can be used to implement very low-power and high-speed links.<\/p>\n<\/td>\n<\/tr>\n

\n

Short Reach Transceiver Design Tradeoffs
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.<\/p>\n<\/td>\n<\/tr>\n

\n

Tradeoffs in Design of Slicers
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.<\/p>\n<\/td>\n<\/tr>\n

\n

Discrete-Time Front-End Design
\nArmin Tajalli, University of Utah, USA
\n<\/b><\/p>\n

Design of high-speed front-end circuits, especially for receivers, is becoming more and more challenging. The need for more complex equalization schemes highlights the importance of designing very high-speed continuous-time and discrete-time circuits. The main focus of this lecture will be on circuit topologies that modern receivers use to extend their bandwidth and functionality. The lecture will start with a short introduction on a novel design algorithm to maximize the speed and energy-efficiency of analog circuits, followed by introducing several new circuit topologies for implementing DFEs.<\/p>\n<\/td>\n<\/tr>\n

\n

Baud-Rate CDRs
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Introduction to PAM4 signaling
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

PAM4 signaling format will be introduced and the design challenges associated with both transmitter, receivers and equalizers will be presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Trans-Impedance Amplifiers
\nPavan Hanumolu, University of Illinois, USA
\n<\/b><\/p>\n

Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.<\/p>\n<\/td>\n<\/tr>\n

\n

Optical Transmitters
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and supercomputers. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.<\/p>\n<\/td>\n<\/tr>\n

\n

Design of ADC-Based Serial Links
\nSam Palermo, Texas A&M University, USA
\n<\/b><\/p>\n

This talk provides an overview of key concepts in ADC-based serial links that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, modeling approaches, and calibration techniques.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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