{"id":5125,"date":"2020-04-22T06:58:01","date_gmt":"2020-04-22T06:58:01","guid":{"rendered":"http:\/\/mead.ch\/mead\/?p=5125"},"modified":"2025-06-23T08:33:17","modified_gmt":"2025-06-23T08:33:17","slug":"delta-sigma-data-converters-3","status":"publish","type":"post","link":"https:\/\/mead.ch\/mead\/delta-sigma-data-converters-3\/","title":{"rendered":"Delta-Sigma Data Converters"},"content":{"rendered":"

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Abstracts<\/a>Practical Information<\/a>Course Material<\/a><\/div>\n

On-Line Class
CET – Central European Time Zone
<\/span><\/h3>\n

Download One-Page Schedule Here<\/a><\/p>\n\n\n\n
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Week 1: June 1-5, 2026<\/h4>\n

Week 2: June 8-12, 2026<\/h4>\n

Registration deadline: May 18, 2026<\/strong><\/span>
Payment deadline: May 22, 2026<\/strong>
<\/span><\/p>\n<\/td>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
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TEACHING HOURS
<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

DAILY<\/td>\nCentral European Time CET<\/strong><\/td>\nEastern Standard Time EST<\/strong><\/td>\nPacific Standard Time PST<\/strong><\/td>\nIndia Standard Time IST<\/strong><\/td>\n<\/tr>\n
Module 1<\/td>\n3:00-4:30 pm<\/td>\n9:00-10:30 am<\/td>\n6:00-7:30 am<\/td>\n6:30-8:00 pm<\/td>\n<\/tr>\n
Module 2<\/td>\n5:00-6:30 pm<\/td>\n11:00 am-12:30 pm<\/td>\n8:00-9:30 am<\/td>\n8:30-10:00 pm<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 1: June 1-5, 2026<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Monday, June 1<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nDelta Sigma Converter Basics \u2013 Parts A & B<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Tuesday, June 2<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nDelta Sigma Converter Basics \u2013 Parts C & D<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Wednesday, June 3<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\n\n

Delta Sigma Converter Basics \u2013 Part E<\/p>\n<\/td>\n

Shanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\n\n

High-Level Design of CT-Delta Sigma Modulators<\/p>\n<\/td>\n

Shanthi Pavan<\/td>\n<\/tr>\n
\n

Thursday, June 4<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\n\n

Discrete-Time Delta Sigma Design<\/p>\n<\/td>\n

David Johns<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\n\n

Incremental and Sensor ADCs<\/p>\n<\/td>\n

David Johns<\/td>\n<\/tr>\n
\n

Friday, June 5<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-6:30 pm<\/td>\nLow-Power Opamp Design<\/td>\nDavid Johns<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

WEEK 2: June 8-12, 2026<\/strong><\/span><\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
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Monday, June 8<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nCircuit Techniques to Mitigate Flicker Noise in CTDS Modulators<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nNon-Idealities in Continuous-Time DS Modulators<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Tuesday, June 9<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nDesign of Building Blocks for CTDSM Modulators – Part 1<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nDesign of Building Blocks for CTDSM Modulators – Part 2<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Wednesday, June 10<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nSystematic Design Centering of a Practical CTDSM<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nFIR Feedback in CTDSMs<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Thursday, June 11<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nIntroduction to Dynamic Element Matching and Calibration<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nCascaded Continuous-Time Delta-Sigma Converters<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\n

Friday, June 12<\/strong><\/span><\/h4>\n<\/td>\n<\/tr>\n

3:00-4:30 pm<\/td>\nCase Studies :\u00a0Part 1<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
5:00-6:30 pm<\/td>\nCase Studies :\u00a0Part 2<\/td>\nShanthi Pavan<\/td>\n<\/tr>\n
\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n

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<\/a><\/p>\n

Abstracts<\/strong><\/span><\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

Delta-Sigma Data Converters
On-Line Class, <\/b>June 1-12, 2026<\/b><\/p>\n<\/td>\n<\/tr>\n

\u00a0<\/td>\n<\/tr>\n
\n

Delta Sigma Converter Basics, Parts A & B
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Review of quantization noise, oversampling and noise shaping. High order delta-sigma loops and \u00a0Signal dependent\u00a0stability.<\/p>\n<\/td>\n<\/tr>\n

\n

Delta Sigma Converter Basics, Parts C, D & E
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Fundamental tradeoffs in DS modulators – maximum stable amplitude and\u00a0noise shaping. Loop filter topologies for discrete-time delta-sigma converters. Simulation techniques for Delta-Sigma Modulators: windowing and spectral estimation.<\/p>\n<\/td>\n<\/tr>\n

\n

High-Level Design of\u00a0Continuous-Time Delta-Sigma Modulators<\/b>
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Systematic design of Continuous-Time Delta-Sigma Modulators from the DT prototype using z-transform and state space methods. The “method of moments” approach to design and intuitive understanding of Continuous-Time Delta-Sigma Modulators.<\/p>\n<\/td>\n<\/tr>\n

\n

Discrete-Time Delta-Sigma Design
David Johns, University of Toronto<\/b><\/p>\n

This talk will discuss the design of switched-capacitor delta sigma design. The basics of switched-capacitor circuits will be presented as well as circuit approaches to overcome limitations. In addition, the design of delta sigma converters using switched capacitor circuits will be discussed with the use of an example design.<\/p>\n<\/td>\n<\/tr>\n

\n

Incremental and Sensor ADCs
David Johns, University of Toronto<\/b><\/p>\n

This talk will discuss the design of incremental ADCs as well as low-frequency sensor data converters. These goal of these converters are to not only have high linearity and SNR but also to have low offset and high accuracy.<\/p>\n<\/td>\n<\/tr>\n

\n

Low-Power Opamp Design
David Johns, University of Toronto<\/b><\/p>\n

To optimize power in opamp design, one must be familiar with a variety of issues. This lecture will cover weak\/mid\/strong-inversion biasing with a focus on when and where each are used in a design. Also discussed will be rapid circuit analysis techniques as well as covering design optimization for 2-stage and folded-cascode opamps.<\/p>\n<\/td>\n<\/tr>\n

\n

Circuit Techniques to Mitigate Flicker Noise in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Flicker noise reduction in CTDSMs using chopping. Intuition behind the effect of chopping in CTDSMs. Circuit techniques that address chopping artifacts in CTDSMs.<\/p>\n<\/td>\n<\/tr>\n

\n

Non-idealities in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Excess loop delay, and compensation techniques. Clock jitter and metastability. Clock jitter and metastability (contd). Mitigating effects of jitter in CTDSMs. Time constant variations. Loop filter nonlinearity.<\/p>\n<\/td>\n<\/tr>\n

\n

Design of Building Blocks for Continuous-Time Delta-Sigma Modulators<\/b>
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Circuit techniques for the design of integrators, latches and flash ADCs, DACs – resistive, and current steering.<\/p>\n<\/td>\n<\/tr>\n

\n

Systematic Design Centering a Practical Continuous-Time Delta-Sigma Modulator
Shanthi Pavan, Indian Institute of Technology<\/b><\/p>\n

Techniques for accounting for excess delay, finite OTA gain and bandwidth and layout parasitics in a CTDSM.<\/p>\n<\/td>\n<\/tr>\n

\n

FIR Deedback in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology
<\/b><\/p>\n

The motivation behind FIR feedback in CTDSMs. Principle behind compensation for FIR DAC delay.<\/p>\n<\/td>\n<\/tr>\n

\n

Introduction to Dynamic Element Matching and Calibration
Shanthi Pavan, Indian Institute of Technology
<\/b><\/p>\n

Analysis of element mismatch in multibit DACs. Techniques to mitigate DAC mismatch problems. Data-weighted averaging and tree-structured mismatch shaping.<\/p>\n<\/td>\n<\/tr>\n

\n

Cascaded Continuous-Time Delta-Sigma Converters (Module 2)
Shanthi Pavan, Indian Institute of Technology
<\/b><\/p>\n

Motivation behind CT-MASH ADCs. CT-MASH ADC topologies. Interstage noise cancellation. Practical techniques for simulating CT-MASH converters.<\/p>\n<\/td>\n<\/tr>\n

\"registration\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Scroll to Top<\/a><\/p>\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

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