Week 1: May 12-16, 2025

Week 2: May 19-23, 2025

Registration deadline: April 28, 2025
Payment deadline: May 2, 2025

TEACHING HOURS

Monday, May 12

Tuesday, May 13

Wednesday, May 14

Thursday, May 15

Friday, May 16

Monday, May 19

Tuesday, May 20

Wednesday, May 21

Thursday, May 22

Friday, May 23

Wireline SERDES Transceivers
On-Line Class
May 12-23, 2025

Introduction to Wireline Transceivers
Pavan Hanumolu, University of Illinois, USA

An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.

Transmitters (CML/VM)
Pavan Hanumolu, University of Illinois, USA

Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.

FIR Equalizers (Tx/Rx)
Pavan Hanumolu, University of Illinois, USA

Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described

Receivers (CTLE, DFE, Adaptation)
Pavan Hanumolu, University of Illinois, USA

Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.

Phase-Locked Loops
Pavan Hanumolu, University of Illinois, USA

Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type – II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.

Clock and Data Recovery
Pavan Hanumolu, University of Illinois, USA

Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.

Phase/Frequency Detectors
Pavan Hanumolu, University of Illinois, USA

This module discusses several phase and frequency detector architectures used in modern clock and data recovery circuits. The advantages and drawback of each of the detectors will be described. Circuit implementation details will be presented.

Advanced CDRs
Pavan Hanumolu, University of Illinois, USA

This module builds on the basic CDR topology and describes architectures that can overcome fundamental jitter tolerance/transfer tradeoffs. Detailed analysis and implementation details will be presented.

Baud-Rate CDRs
Pavan Hanumolu, University of Illinois, USA

Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.

Trans-Impedance Amplifiers
Pavan Hanumolu, University of Illinois, USA

Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.

Advanced Signaling Methods
Armin Tajalli, University of Utah, USA

Moving toward data rates beyond 56 Gb/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Chordal codes, that can be used to implement very low-power and high-speed links.

Short Reach Transceiver Design Tradeoffs
Armin Tajalli, University of Utah, USA

Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.

Tradeoffs in Design of Slicers
Armin Tajalli, University of Utah, USA

Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.

Discrete-Time Front-End Design
Armin Tajalli, University of Utah, USA

Design of high-speed front-end circuits, especially for receivers, is becoming more and more challenging. The need for more complex equalization schemes highlights the importance of designing very high-speed continuous-time and discrete-time circuits. The main focus of this lecture will be on circuit topologies that modern receivers use to extend their bandwidth and functionality. The lecture will start with a short introduction on a novel design algorithm to maximize the speed and energy-efficiency of analog circuits, followed by introducing several new circuit topologies for implementing DFEs.

Optical Transmitters
Sam Palermo, Texas A&M University, USA

This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and high-performance computing systems. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.

ADC-Based RX Analysis and Digital Equalization
Sam Palermo, Texas A&M University, USA

This talk provides an overview of key concepts in ADC-based serial link receivers that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, and modeling approaches.

Wireline RX Time-Interleaved ADC Design and Calibration
Sam Palermo, Texas A&M University, USA

This talk provides an overview of the high-speed time-interleaved ADCs that are now becoming prevelant in high-performance wireline receivers. The design of high-speed sample and hold topologies, key flash and SAR ADC circuits, and advanced ADC techniques is covered. The impact of time-interleaving errors and calibration techniques are also presented.

DSP-DAC Wireline Transmitters
Sam Palermo, Texas A&M University, USA

This talk provides an overview of key concepts in DAC-based serial link transmitters that support operation over high-loss channels. Topics covered include trade-offs between analog and DAC-based transmitters, key performance metrics, high-speed current-mode and voltage-mode DAC design techniques, and DSP-based transmit equalizers.