June 17-21, 2024

Registration deadline: May 17, 2024
Payment deadline: June 7, 2024

Downloard one-page schedule here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 17

TUESDAY, June 18

WEDNESDAY, June 19

THURSDAY, June 20

FRIDAY, June 21

Practical Design of Data Converters
June 17-21, 2024
EPFL Premises, Lausanne, Switzerland

Basic ADC Topologies and Specifications: Overview
Marcel Pelgrom, Pelgrom Consult, The Netherlands

After an introduction in the fundamental limits given by timing and component accuracy, the basic architectures of ADCs and DACs are reviewed and the main characteristics indicated. A glossary of specification definitions is presented along with practical tips to evaluate these specifications.

ADCs Comparators
Marcel Pelgrom, Pelgrom Consult, The Netherlands

The design of a comparator is often the starting point of an ADC. Comparators determine various performance parameters, like Bit-Error Rate, speed and accuracy. These aspects are analyzed and illustrated on a comparator catalog: ten published comparators will be discussed with their merits and disadvantages.

Time Interleaved ADCs
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Using time-interleaving of relatively slow analog-to-digital converters allows achieving high-speed conversion at moderate resolution. The main problem that is encountered in this type of converters is related to various forms of mismatch. Offset, gain and skew variations create various artifacts and need often calibration. After a theoretical overview, the practical aspects of time-interleaved conversion will be discussed. A number of designs are analyzed for the merits.

Limits of Nyquist ADC Architectures
Filip Tavernier, KU Leuven, Belgium

Getting the maximum speed and accuracy for the minimum power consumption is crucial in every ADC design. This multi-dimensional problem requires careful consideration of many different aspects, from the ADC architecture to the technology at hand, to achieve optimal results.
This talk starts by reviewing the recent state-of-the-art of major ADC architectures, such as flash, SAR, pipeline, and pipelined-SAR. After describing their respective operation principles, it provides a quantitative comparison of their accuracy — speed — power limits, offering insight into the architectures’ and the individual blocks’ contributions. This comparison is extended by including process effects over four deep-scaled CMOS process nodes, building unique insight into both architectural as well as technological capabilities.

Case Study of a High-Speed Single-Channel SAR ADC
Filip Tavernier, KU Leuven, Belgium

This lecture starts with an overview of speed-enhancement techniques of SAR ADCs. Next, it discusses the design and measurement of a 1.25 GS/s 7-b single-channel SAR ADC that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist.

Case Study of a Time-Interleaved Hybrid ADC
Filip Tavernier, KU Leuven, Belgium

ADCs with high-resolution (>10 bit), multi-GHz sample rate/bandwidth, and low power are critical components in modern communication and instrumentation systems to enable direct RF sampling. Time-interleaved (TI) RF ADCs have been extensively employed to allow these specifications. However, TI ADCs come with interleaving mismatches, namely offset, gain, timing, and bandwidth. Further, additional design overhead results from the input front-end loading, routing, clock generation/distribution, and calibration circuitry to compensate for interleaving mismatches. Hence, the interleaving factor and sub-ADC architecture become critical choices in realizing an efficient-sub-ADC and minimizing interleaving overhead to achieve optimal performance.
This talk reviews time interleaving as a popular way of extending the speed of standalone ADCs and focuses on some key aspects such as interleaving errors and interleave architectures, discussing their trade-offs. To illustrate this, the design of a state-of-the-art 8x-interleaved 5 GS/s 12 bit hybrid three-stage pipelined-SAR with analog/digital corrections is presented.

Oversampling ADCs :
Discrete-and-Continuous-time Delta-Sigma Converters
Shanthi Pavan, Indian Institute of Technology, India

Overview of oversampling and noise shaping, birds-eye view of design trade offs in delta-sigma data converters, discrete-time and continuous-time delta-sigma.

Case Study: Low-Power Data Converters (1 & 2)
Kofi Makinwa, TU Delft, Belgium

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Simulating ADCs: Frequency Domain:
FFT, Bin Choice, Windowing, Noise Level, kT/C Noise
Shanthi Pavan, Indian Institute of Technology, India

ADC simulation in the frequency domain. FFT overview, choice of input frequency, cohorent and incohorent sampling, windowing.

Continuous-Time Pipeline ADC
Shanthi Pavan, Indian Institute of Technology, India

Abstract to come.

Current Steering DAC’s
Klaas Bult, Analog Design Consult, The Netherlands

Current Steering is the architecture of choice when it comes to high speed, high performance DACs. This lecture will start completely from scratch and detail all the design aspects of current steering DACs. DAC design comes down to knowing the many different error mechanisms there are and knowing the counter measures that exist in order to get good performance, even at high frequencies.

Mismatch Shaping Multi-bit DACs
Ian Galton, UC San Diego, USA

Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

Simulating Sigma-Delta Converters
Shanthi Pavan, Indian Institute of Technology, India

Simulation of discrete- and continuous-time delta-sigma converters. The impulse-invariant transformation, the delta-sigma toolbox for MATLAB. Systematic design centering of a practical continuous-time delta-sigma converter, rapid estimation of signal and noise transfer function of a practical DSM design.

Case Study:
High-Performance Delta Sigma Converter
Shanthi Pavan, Indian Institute of Technology, India