June 17-21, 2024

Registration deadline: May 17, 2024
Payment deadline: June 7, 2024

Download One-Page Schedule Here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 17

TUESDAY, June 18

WEDNESDAY, June 19

THURSDAY, June 20

FRIDAY, June 21

Low-Power Analog Circuit Design
June 17-21, 2024
EPFL Premises, Lausanne, Switzerland

MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design
Christian Enz, EPFL

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.

Design of Low-power Analog Circuits using the Inversion Coefficient
Christian Enz, EPFL

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.

Noise Performance of Elementary Circuit Blocks
Boris Murmann, University of Hawaii

Designing energy-energy efficient analog circuits requires a solid understanding of electronic noise. The material covered in these two modules requires no prerequisite knowledge and looks at shot noise (due to discreteness as charge) as an intuitive baseline for further treatment. After modeling thermal and 1/f noise at the device level, we analyze its impact on elementary circuits such as common source/gate/drain amplifiers as well as switched capacitor structures. We then expand the treatment to feedback circuits with an emphasis on sensor front ends. Lastly, we analyze noise in filters and the noise penalty paid for emulating inductors using active circuits.

Opamp Topologies and Design Fundamentals
Boris Murmann, University of Hawaii

While there exist a myriad of topologies and design tricks for integrated opamps, these two introductory modules intend to untangle the design space with an emphasis on the fundamentals. Covered topics will include: (1) Elementary building blocks operated at low supply voltage and/or low current: Current mirrors, differential pairs, inverter-based stages, low-voltage cascode configurations; (2) Basic topologies: Telescopic, folded-cascode, and multi-stage; (3) Stability and frequency compensation techniques; (4) fully differential implementation and common-mode feedback.

Low-Power High Efficiency OpAmp Design
Klaas Bult, Analog Design Consult

The goal of this lecture is to find the relationship between circuit performance and power dissipation. As an example, a commonly-used OpAmp is analysed and expressions are found that give detailed insight into what power dissipation is needed to obtain a certain performance. The result is simple expression that show power dissipation as a function of performance parameters.

Low-Power High Efficiency Residue Amplifiers
Klaas Bult, Analog Design Consult

In the past 1.5 decade, residue amplifiers have shown a remarkable 50-fold reduction in power dissipation. The findings of the previous lecture are being used to explain this reduction, through a step-by-step analysis that details which circuit techniques enabled this power reduction.

Analog Design Methodology and Practical Techniques for Frequency Compensation
Vadim Ivanov, Texas Instruments

Abstract.

Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources
Vadim Ivanov, Texas Instruments

Discussed are principles of the voltage reference generation, primarily of the bandgap voltage references, its error sources and techniques for improving accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; layout and packaging; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption. Considered are biasing cores, power-on resets, design of the mirror trees and circuit techniques for current source generation with high impedance and wide voltage range.

Power Dissipation in ADC Buidling Blocks
Klaas Bult, Analog Design Consult

Choosing the correct ADC architecture is the most powerful means to obtain low power dissipation. Finding expressions for the power dissipation of all ADC building blocks, is a first step in that direction. Using the same technique described in the lecture “Low Power High Efficiency OpAmp Design”, the most common ADC building block are analysed and expressions are found for power dissipation, as a function of their performance parameters.

Power Dissipation in ADCs
Klaas Bult, Analog Design Consult

This lecture builds on the findings of the lecture “Power Dissipation in ADC Building Blocks” and uses the results found in that lecture to come to estimations of power dissipation of various kinds of ADC architectures, dependent on their performance. A comparison is made between these estimates and the results that can be found in published results.

Micropower ADCs
Kofi Makinwa, TU Delft

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Energy Efficient Sensor Interfaces
Taekwang Jang, ETHZ

Abstract.

Low-Power Frequency Reference Circuits
Taekwang Jang, ETHZ

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
In this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.

Power Management With Nanoampere Consumption and Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments

Abstract.