April 20-24, 2020

Registration deadline: March 20, 2020
Payment deadline: April 13, 2020

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, April 20: Introduction and Overview

TUESDAY, April 21: Physical Sensors

WEDNESDAY, April 22: Sensor Systems and Modeling

THURSDAY, April 23: Sensor Systems and Interfaces

FRIDAY, April 24: Sensor Systems for Imaging

SMART SENSOR SYSTEMS
APRIL 20-24, 2020
TUDelft, Delft, The Netherlands

Designing Smart Sensor Systems
Kofi Makinwa, TU Delft, the Netherlands

Smart Sensor Systems are systems in which sensors and dedicated interface electronics are integrated on the same chip, or at least in the same package. The design of such sensors requires a multidisciplinary approach that takes the characteristics and requirements of the whole system into account. The interface electronics needs to be designed in such a way that it does not limit sensor performance. Since sensors are often relatively slow, the necessary precision can often be achieved by the use of dynamic techniques such as chopping, auto-zeroing and dynamic element matching. As an example, the design of a state-of-the-art wind sensor will be described.

Measurement and Calibration Techniques
Michiel A.P. Pertijs, TU Delft, the Netherlands

This lecture discusses the basics of measurement and calibration. Calibration procedures are essential for establishing the accuracy of a sensor in relation to standards. The lecture discusses how smart sensors differ from conventional sensors in how they are calibrated and how they are used after calibration. Various calibration techniques are introduced, as well as various trimming and correction techniques that can be used to adjust smart sensors after calibration. The lecture also explores the possibility of realizing self-calibrating smart sensors. Various forms of self-calibration are discussed, including the co-integration of additional sensors to compensate for cross-sensitivity, and the co-integration of an actuator to generate a calibration signal locally. Three case studies, of a smart temperature sensor, a smart wind sensor and a self-calibrating Hall sensor, are included to illustrate the various concepts.

Analog-to-Digital Converters
Marcel Pelgrom, Pelgrom Consult, the Netherlands

The basic principles of analog-to-digital conversion will be discussed as well as some characteristic parameters. Different conversion architectures allow optimum conversion for various signal types. Often the trade-off is between accuracy, bandwidth and power. In this lecture specific attention is given to successive approximation and sigma delta conversion. Some practical examples will illustrate the concepts.

Dynamic Offset-Cancellation Techniques
Kofi Makinwa, TU Delft, the Netherlands

In modern CMOS processes, device mismatch typically results in offset voltages of several millivolts. But many sensor interfaces require much lower offset levels. By using dynamic offset cancellation techniques such as auto-zeroing and chopping, however, microvolt levels of offset can be routinely achieved. In this lecture, an introduction to the theory of auto-zeroing and chopping will be given, and the pros and cons of both techniques will be discussed. Examples will be given of the use of auto-zeroing and chopping in sensor interfaces with residual offsets as low as 50nV.

CMOS-Compatible Microfabrication
Reinoud Wolffenbuttel, TU Delft, the Netherlands

A CMOS chip containing both the sensor and electronic circuits is the ultimate level of integration of a Smart Sensor System. However, wafer-level co-fabrication requires full compatibility between the dedicated processing of the sensors and the main process flow for the circuits. Some transduction effects, such as utilization of the temperature dependence of CMOS components, come for free with the mainstream CMOS process. Other effects intrinsic to operation of CMOS components, such as photo-electric effects in diodes, can be exploited using a non-conventional mask design. However, in the general case departures from the mainstream CMOS process are required for including sensor functionality. Any additional sensor-related processing makes the CMOS process non-standard and care should be taken to ensure proper operation of the circuits. Compatibility requirements forces to strategic decisions: on the economic viability of the on-chip integration in the intended application, but also on whether to postpone sensor-related processing until after completion of the CMOS processing or to interrupt the main process flow. Compatibility of process steps also results in limitations, such as: acceptable materials, etchants (for cleanroom re-entrance) and conditions (maximum anneal for circuit operation). The various approaches for CMOS-compatible integration are discussed, with an emphasis on CMOS-compatible micromachining using examples of successfully integrated single-chip microsystems.

Smart Inertial Sensors
Michael Kraft, KU Leuven, Belgium

Accelerometers and gyroscopes are one of the most successful MEMS sensors. The lecture will briefly present their underlying principles, and then focus on the state-of-the-art as there is still considerable effort going on to increase their performance and functionality. Key to high performance is the inclusion of micromachined sensing element in a force-feedback, closed loop control system. The approach based on electro-mechanical sigma-delta modulator has proven to be very successful in recent years. Such a control system yields a digital output enabling the digital processing of the sensors’ output, hence allowing the design of smart inertial sensors.

Integrated Hall Magnetic Sensors
Pavel Kejik, EPFL, Lausanne, Switzerland

The lecture starts with a brief introduction into the Hall effect and Hall elements. Then the problems and good practices in the realization of integrated Hall magnetic sensors will be reviewed. The main issues are offset, temperature cross-sensitivity, switching noise, and drift related to the packaging stress. By combining Hall elements with well-adapted interface electronics some of the problems can be dramatically reduced. It will be shown that integration of magnetic flux concentrators on the sensor chip will further decrease the equivalent magnetic noise and offset.

Smart Temperature Sensors
Kofi Makinwa, TU Delft, the Netherlands

Smart temperature sensors are everywhere! They are used in CPUs for thermal management, in DRAMs to control refresh rates, and in MEMS frequency references for temperature compensation, to name but a few high volume applications. In this lecture, the operating principles of smart temperature sensors will be explained, their main sources of inaccuracy identified, and suitable remedies, at the device, circuit and system levels, described. To further illustrate these concepts, the design of state-of-the-art temperature sensors with inaccuracies in the order of 0.1°C will be presented.

Implantable Smart Sensors for Advanced Medical Devices
Tim Denison, Medtronic Neuromodulation, USA

The use of physiological sensors is a key enabling technology for implementing ‘smart’ implantable systems. For example, electrocardiograms (ECG) are well established for measuring the intrinsic activity of the heart, and algorithms based on the ECG help to initiate stimulation therapy in the presence of an abnormal beat in modern pacemakers. The role of physiological sensing continues to grow as technology evolves and can be applied to resolving unmet clinical needs. The practical implementation of chronic physiological sensors presents numerous challenges. In particular, sensors that go in the body have strict requirements on reliability, stability and safety. Additional challenges arise with the constraints placed on an implantable design. These constraints include low supply overhead and limited current drain, as chronic sensors must often limit their power dissipation to microwatt levels in order to have acceptable implant longevity. This tutorial will highlight recent physiological smart sensor prototypes that provide robust performance within the constraint of an implantable system. Case studies will include “reflex concepts” implemented with accelerometers, as well as prototype seizure monitors and prosthetic brain-machine interface technologies utilizing precision chopper amplifiers.

CMOS-based DNA Microarrays
Roland Thewes, TU Berlin, Germany

CMOS-based DNA sensor arrays have gained huge interest in recent years since they provide advantages compared to state-of-the-art commercially available tools for the same purpose using optical principles. In this lecture, an overview is given starting with the general operation principle of DNA microarrays, optical and electronic functionalization techniques, and detection principles using labeling-based and label-free read-out. CMOS integration issues and the related processing requirements are briefly discussed. Emphasis is put on CMOS circuit design requirements in terms of sensitivity, stability, and further parameters depending on the particular application. Examples from the literature are considered to demonstrate opportunities and limitations of CMOS chips applied in that field.

Guided Simulation on Multi-Domain Modeling
Ger de Graaf, TU Delft, the Netherlands

This guided tutorial is intended to provide each individual participant with hands-on experience in the use of a finite element-based multi-physics simulation tool (COMSOL Multiphysics) that has become indispensable in smart sensor design. The simulation is organised in two inseparable sessions. During the first session the essentials of multi-domain modelling in the coupled thermal-electrical domains are highlighted, first in terms of equivalent lumped components and followed by the representation that is suitable for finite element modelling. Subsequently, the modelling is applied for analysing the thermal behaviour of a free-standing micro-beam with an electrical current applied. The step-wise guided simulation confronts each participant with practical issues, such as meshing, applying proper boundary conditions, use of a material database and post processing of the results. Finally operation as a CMOS-compatible hot-wire anemometer is verified. The second session is dedicated to the design of a bulk-micromachined accelerometer.  After the presentation of the mechanical-electrical coupled domains, the equivalent lumped components and the hands-on building of the finite element model, participants are guided through several accelerometer designs aspects, such as bandwidth, higher-order modes of operation and squeeze-film air damping.

Precision Instrumentation Amplifiers
Johan Huijsing, TU Delft, the Netherlands

To understand the problems of the designers of sensor interface circuits will help the system designer to get the best performance. The principles and features of precision instrumentation amplifiers, key building blocks of many sensor interfaces, will be discussed from a designer’s point of view. Constraints regarding noise, dynamic range, common-mode range will be discussed for circuits made in state-of-the art technology. The case studies include instrumentation amplifiers with offset cancellation, and amplifiers with rail-to-rail voltage ranges.

References for Smart Sensors
Fabio Sebastiano, TU Delft, The Netherlands

Although often neglected, a reference is always required for any measurements, since measuring basically involves comparing the physical parameter of interest to a known quantity. Consequently, it is a fundamental component in any smart sensor, which can even limit the performance of the whole system if not properly designed. In this lecture, an overview of references for smart sensors will be given with specific focus on references that can be implemented on chip in a standard CMOS process. An overview of references available in CMOS will be presented, including resistance, capacitive, voltage, current and frequency references. We will discuss the need for references in smart sensors and their requirements, and explore through practical examples and case studies how the performance of integrated references can meet those requirements.

Multi-Electrode Capacitive Sensors
Gerard C.M. Meijer, TU Delft, the Netherlands

A systematic approach towards the design of reliable smart low-cost high-performance capacitive sensors is presented. The basis problems and their solutions of both the physical and the electrical signal processing are discussed. The examples concern capacitive sensors in position detectors, liquid-level detectors and personnel detectors.

Smart Acoustic Sensors
Michiel A.P. Pertijs, TU Delft, the Netherlands

Acoustic waves can be used to perform a wide variety of measurements, such as flow sensing, ranging and medical imaging. This lecture first introduces the basic operating principles of acoustic sensors and then focuses on the opportunities opened up by combining transducers and integrated electronics to form smart acoustic sensors. This combination is key for the realization of ultrasonic devices that employ transducer arrays with large numbers of elements, e.g. for 3D medical imaging, and for miniaturized, low-power devices. The basic operating principles of piezo-electric and capacitive ultrasound transducers and key interface circuits such as LNAs, pulsers and beamformers will be discussed. A miniature ultrasound probe for 3D medical imaging will presented as a case study.

CMOS Image Sensor
Albert Theuwissen, Harvest Imaging, the Netherlands

Today, image sensors are present in a wide variety of applications, such as picture taking, video capture, medical imaging, scientific instrumentation and machine vision. Image sensors are used as one of the key input devices for highly automated systems, such as self driving cars or order picking robots. Most image sensors are built in CMOS technology, because it allows to optimize the image sensor for the required specifications and to implement the required functionality in a power- and cost-efficient way. This presentation will give an overview of CMOS image sensors and pixels, readout circuit architectures, manufacturing technologies and key image sensor specifications. New applications are demanding specific requirements to the image sensor, of which some examples will be elaborated.

September 7-11, 2020

Registration deadline: July 17, 2020
Payment deadline: August 17, 2020

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, September 7

TUESDAY, September 8

WEDNESDAY, September 9

THURSDAY, September 10

FRIDAY, September 11

HIGH-PERFORMANCE DATA CONVERTERS
September 7-11, 2020
EPFL Premises, Lausanne, Switzerland

Overview of High-Speed Data Converters
Marcel Pelgrom, Pelgrom Consult, The Netherlands

High-speed data converters are the basic ingredient in many data conversion techniques. Technology and design choices influence the way a converter can achieve its performance goals. In this overview the basic sampling and quantization mechanisms will be reviewed followed by some techniques to circumvent or reduce unwanted effects.

Fundamental Limitations
Marcel Pelgrom, Pelgrom Consult, The Netherlands

Matching of components, noise, distortion and jitter are the dominant factors that limit high-speed converter performance. Technology and design choices influence the way these limitations appear in the final conversion result. The basic mechanisms will be discussed and techniques to circumvent or reduce unwanted effects will be presented.

Flash ADCs
Marcel Pelgrom, Pelgrom Consult, The Netherlands

The flash ADC is the basic building block of many ADC topologies. Various aspects of the design of a flash ADC will be considered: ladder impedance, comparator design, decoding and interpolation. The design choices will be illustrated with examples in which also trade-offs on a design level will be considered.

Interleaved ADCs
Marcel Pelgrom, Pelgrom Consult, The Netherlands

The introduction of massive parallel analog-to-digital conversion or interleaved converters, has allowed to process wide bandwidths at moderate resolutions. This talk will survey the theoretical background, the various design choices and the errors caused by unequal parallel paths.

Mismatch-Shaping Multi-bit DACs
Ian Galton, UC San Diego, USA

Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

SAR ADCs
Klaas Bult, Bult Consult, The Netherlands

Dating back to the 1970s, SAR ADCs have once again become popular but for a different reason. It has been recognized that these ADCs better lend themselves to scaled technologies as they employ few analog functions. This presentation deals with the basic properties of SAR ADCs and their pros and cons. It is shown that these architectures can be realized with zero static power consumption but they need complex DACs and suffer from a low speed.

Comparison of ADC Architectures
Klaas Bult, Bult Consult, The Netherlands

In this lecture we will discuss the various architectures (Flash, Folding, SAR, Pipeline, Pipelined-SAR, etc.) and how the building blocks appear in these architectures and which demands these architectures put on these blocks.

Introduction to Pipeline ADCs
Ian Galton, UC San Diego, USA

This lecture presents a detailed introduction to pipelined ADCs. First, the system-level concepts underlying pipelined ADCs are presented in terms of a particular pipelined ADC example, including sensitivity to non-ideal behavior of the various pipeline components. Architectural tradeoffs associated with changing the number of bits per stage and number of stages are then presented. Finally, the specific pipelined ADC example is revisited and circuit-level issues and tradeoffs are introduced.

Pipeline ADCs with Digital Calibration
Ian Galton, UC San Diego, USA

This lecture presents digital background calibration techniques that suppress error introduced by non-ideal analog circuitry. Pipelined ADCs are highly sensitive to mismatches among certain components and residue amplifier gain error and nonlinearity, especially when designed for low supply voltages. The digital calibration techniques address these problems. The system-level concepts and circuit-level implementation issues are presented in the context of a 1.2 V CMOS pipelined ADC design example wherein the techniques are shown to enable state-of-the-art performance.

ADC Building Blocks
Klaas Bult, Bult Consult, The Netherlands

Most ADCs are built from blocks like DACs, Comparators, Amplifiers and logic. We will go into detail on all of these blocks, with different implementations but also very specifically what they have in common. We will also make a fundamental estimate of their power dissipation based on the specifications like for instance Dynamic Range and Sampling Frequency.

Power Dissipation in ADCs (Parts 1 and 2)
Klaas Bult, Bult Consult, The Netherlands

In tese 2 blocks we will discuss the above mentioned architectures and use the Power Dissipation Estimates derived in “ADC Building Blocks” and with that make an estimate of the Power Dissipation of a certain architecture based on it’s specifications. These estimates will be compared to all published ADCs in ISSCC and VLSI of the past 20 years (using the overview that Boris Murmann updates every year on his website). This comparison with real data shows that this method of estimating power yields
very realistic results with numbers close to published data. This method moreover allows us to make estimates of not yet existing ADCs based on their specifications. It allows to make choice between architecture based on it’s performance and expected power dissipation. This will make for a much better starting point than what is usually the case in real designs.

VCO-Based ADC Techniques
Ian Galton, UC San Diego, USA

ADCs based on ring oscillator voltage controlled oscillators (VCOs) enabled by digital calibration have the functionality of conventional continuous-time delta-sigma ADCs, but without the need for analog integrators, feedback DACs, comparators, reference voltages, or low-jitter clocks. Therefore, they use much less area than comparable conventional delta-sigma ADCs, are well-suited to advanced CMOS technology, and can easily support reconfigurability. This lecture will describe the principles of VCO-based ADCs, their limitations, techniques such as digital calibration for addressing their limitations, and will present case studies of example IC implementations.

DEM for Nyquist-Rate Current-Steering DACs
Ian Galton, UC San Diego, USA

In high-resolution (>11 ENOB) Nyquist-rate DACs, mismatches among nominally identical components incurred during IC fabrication as well as possible systematic circuit and layout mismatches cause harmonic distortion and often limit overall DAC linearity. This talk describes recently-developed segmented DEM techniques applicable to high-resolution Nyquist-rate DACs that eliminate pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion.

High-Speed Digital-to-Analog Converters
Klaas Bult, Bult Consul, The Netherlands

Introduction to current-steering DACs. Common error mechanisms; error sources affecting amplitude and timing. Code dependent output-impedance; solutions, measurements, comparison to theory and literature.

Embedded Analog-to-Digital Converters
Klaas Bult, Bult Consult, The Netherlands

Systems-on-Chips (SoCs) have become a reality in the past decade. Several dozens of different functional blocks are being integrated on a single die, reaching transistors counts of up to half a billion. From the Analog portion of an SoC the Data Converters are probably among the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact that logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. This paper describes these differences and provides an overview of the state-of-the art in Analog-to-Digital Conversion.

June 29 – July 3, 2020

Registration deadline: May 22, 2020
Payment deadline: June 15, 2020

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 29

TUESDAY, June 30

WEDNESDAY, July 1

THURSDAY, July 2

FRIDAY, July 3

Delta-Sigma Data Converters
June 29 – July 3, 2020
EPFL Premises, Lausanne, Switzerland

Delta Sigma Converter Basics, Parts A & B
Shanthi Pavan, Indian Institute of Technology

Review of quantization noise, oversampling and noise shaping. Signal dependent stability, fundamental tradeoffs in DS modulators – maximum stable amplitude and noise shaping.  Simulation techniques for Delta-Sigma Modulators.

Delta Sigma Converter Basics, Parts C, D & E
Shanthi Pavan, Indian Institute of Technology

Abstract to come.

High-Level Design of Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Systematic design of Continuous-Time Delta-Sigma Modulators from the DT prototype using z-transform and state space methods. The “method of moments” approach to design and intuitive understanding of Continuous-Time Delta-Sigma Modulators.

Non-idealities in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Excess loop delay, and compensation techniques. Clock jitter and metastability. Clock jitter and metastability (contd). Mitigating effects of jitter in CTDSMs. Time constant variations. Loop filter nonlinearity.

Design of Building Blocks for Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Abstract to come.

Systematic Design Centering a Practical Continuous-Time Delta-Sigma Modulator
Shanthi Pavan, Indian Institute of Technology

Abstract to come.

Circuit Techniques to Mitigate Flicker Noise in Continuous-Time Delta-Sigma Modulators
Shanthi Pavan, Indian Institute of Technology

Abstract to come.

Dynamic Element Matching (Part 1)
Ian Galton, UC San Diego

Randomization and element rotation techniques. Tree structured mismatch shaping.

Dynamic Element Matching (Part 2)
Ian Galton, UC San Diego

This lecture will explain dynamic element matching (DEM) techniques in general and mismatch-noise shaping DEM in particular. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, DEM DAC topologies and their limitations, DEM encoder algorithms and implementations, and the fundamental performance tradeoffs that govern all types of DEM.

VCO-Based Delta-Sigma ADCs
Ian Galton, UC San Diego

ADCs based on ring oscillator voltage controlled oscillators (VCOs) enabled by digital calibration have the functionality of conventional continuous-time delta-sigma ADCs, but without the need for analog integrators, feedback DACs, comparators, reference voltages, or low-jitter clocks. Therefore, they use much less area than comparable conventional delta-sigma ADCs, are well-suited to advanced CMOS technology, and can easily support reconfigurability. This lecture will describe the principles of VCO-based ADCs, their limitations, techniques such as digital calibration for addressing their limitations, and will present case studies of example IC implementations.

Discrete-Time Delta-Sigma Design
David Johns, University of Toronto

This talk will discuss the design of switched-capacitor delta sigma design. The basics of switched-capacitor circuits will be presented as well as circuit approaches to overcome limitations. In addition, the design of delta sigma converters using switched capacitor circuits will be discussed with the use of an example design.

Introduction to the Delta-Sigma Toolbox
David Johns, University of Toronto

This talk will give an introduction to the use of a Matlab toolbox called the ³Delta Sigma Toolbox². Extensive examples will be given as well as how to make use of state-space to use different filter topologies as well as dynamic range scaling.

Bandpass Delta-Sigma ADCs
David Johns, University of Toronto

This talk will discuss the design of Bandpass Delta Sigma ADCs which are useful in RF systems. Topics covered include resonator structures, architecture choices and example systems.

Incremental and Sensor ADCs
David Johns, University of Toronto

This talk will discuss the design of incremental ADCs as well as low-frequency sensor data converters. These goal of these converters are to not only have high linearity and SNR but also to have low offset and high accuracy.

Circuit Noise Issues with ADCs
David Johns, University of Toronto

This talk will discuss noise in basic circuits and opamps as well as a simple switched-C integrator as they apply to data converters. Topics covered include device noise basics, amplifier/cascode/mirror/diff-pair noise, switched-C noise, and oversampling.