Basics in RF Design
On-Line Class
CET – Central European Time Zone
Download One-Page Schedule Here
Week 1: June 23-27, 2025Week 2: June 30 – July 4, 2025Registration deadline: June 9, 2025 |
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TEACHING HOURS
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| DAILY | Central European Time CET | Eastern Standard Time EST | Pacific Standard Time PST | India Standard Time IST |
| Module 1 | 3:00-4:30 pm | 9:00-10:30 am | 6:00-7:30 am | 6:30-8:00 pm |
| Module 2 | 5:00-6:30 pm | 11:00-12:30 am | 8:00-9:30 am | 8:30-10:00 pm |
WEEK 1: June 23-27, 2025
Monday, June 23
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| 3:00-4:30 pm | Introduction to Wireless RX and TX | Antonio Liscidini |
| 5:00-6:30 pm | Integrated Mixers | Antonio Liscidini |
Tuesday, June 24
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| 3:00-4:30 pm | Base Band Filters | Antonio Liscidini |
| 5:00-6:30 pm | LNA Topologies | Antonio Liscidini |
Wednesday, June 25
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| 3:00-4:30 pm | Wireless CMOS Receiver Front-End Systems | Michiel Steyaert |
| 5:00-6:30 pm | Wireless CMOS Receiver Front-End Circuits | Michiel Steyaert |
Thursday, June 26
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| 3:00-4:30 pm | RF CMOS LNA Topologies | Michiel Steyaert |
| 5:00-6:30 pm | Up-Converters and Single Chip Transceivers | Michiel Steyaert |
Friday, June 27
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| 3:00-4:30 pm | Fundamentals of Analog PLLs | Michiel Steyaert |
| 5:00-6:30 pm | Interference Effects in PLLs | Michiel Steyaert |
WEEK 2: June 30 – July 4
Monday, June 30
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| 3:00-4:30 pm | PLL Building Blocks | Sam Palermo | ||
| 5:00-6:30 pm | PLL Analysis and Modeling | Sam Palermo | ||
Tuesday, July 1
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| 3:00-6:30 | Spiral Inductor Interference, Deadzone and Phase Noise | Michiel Steyaert | ||
Wednesday, June 2
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| 3:00-4:30 pm | Integrated Power Amplifiers (PA): System Level | Patrick Reynaert | ||
| 5:00-6:30 pm | Integrated PA: Classes and Topologies | Patrick Reynaert | ||
Thursday, June 3
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| 3:00-4:30 pm | Integrated PA: Design and Implementation | Patrick Reynaert | ||
| 5:00-6:30 pm | Integrated PA: Stability and Layout | Patrick Reynaert | ||
Friday, June 4
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| 3:00-4:30 pm | Integrated PA: Design at mm-Wave Frequencies | Patrick Reynaert | ||
| 5:00-6:30 pm | Integrated PA: Broadband Design with Transformers | Patrick Reynaert | ||
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Abstracts
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Basics in RF Design |
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Building Blocks and Sub System for Wireless Transceivers (4 modules) After a first introduction of the requirements of a wireless transceiver, the main building blocks and sub-systems will be analyzed with some emphasis on of ultra-low power techniques for IoT applications. On the RF signal path low noise amplifiers, mixer topologies and base band filters will be presented. Beside the most common approaches, particular solutions oriented to ultra-low power systems will be included such as, quadrature low noise amplifiers, self-oscillating mixer, complex/poly-phase filters. |
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Wireless CMOS Receiver Front-End Systems and Circuits Architecture differences towards fully integration CMOS RF implementations. Co-design architecture and mixer topologies. Basic mixer structures, sub-sampling topologies, square-law related topologies and linear down conversion mixers. Quadrature and double quadrature topologies. Poly-phase structures. Design example of a low-IF receiver. |
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RF CMOS LNA Topologies Fundamentals and limits towards CMOS implementations. Common gate, common source with inductive impedance matching, current re-use circuit topologies. Noise figure and non-quasistatic effects. Design examples of low power CMOS LNA’s. |
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Up-Converters and Single Chip Transceivers Quadrature upconverters. Basic mixer structures, linear differential transconductance topologies, single ended circuits and preamplifier buffer stages. Design example of broadband CMOS transmitter circuit. |
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Fundamentals of Analog PLLs Basic definitions and concepts of phase locked loop topologies. Frequency behavior, stability and settling of PLL topologies. Introduction of analog, digital and fractional N synthesizers. Introduction to Phase noise and jitter. |
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Interference Effects in PLLs Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects. |
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PLL Building Blocks This talk covers circuit design techniques for the main building blocks, excluding the VCO, used in analog and digital PLLs. This includes phase detectors, time-to-digital converters, analog and digital loop filters, and high-speed dividers. |
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PLL Analysis and Modeling Abstract. |
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Spiral Inductor Interference, Deadzone and Phase Noise Fundamentals and principles of VCO circuits. Lay-out and design issues of spiral inductors and varactors for CMOS VCO circuits. Effect of loop filter and VCO noise on phase noise behavior of PLL synthesizers. Design examples of fully integrated synthesizers in CMOS technologies. |
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Integrated Power Amplifiers (PA): System Level Abstract |
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Integrated PA: Classes and Topologies Abstract. |
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Integrated PA: Design and Implementation Abstract |
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Integrated PA: Stability and Layout Abstract. |
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Integrated PA: Design at mm-Wave Frequencies Abstract |
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Integrated PA: Broadband Design with Transformers Abstract. |
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