Author Archives: Caroline

    Advanced Analog Circuit Design

    On-Line Class
    PST – California Time Zone

    Download One-Page Schedule Here

    July 13-16, 2020

    Registration deadline: June 17, 2020
    Payment deadline: June 27, 2020

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    TEACHING HOURS

    DAILY Pacific Standard Time PST Eastern Standard Time EST Central European Time CET India Standard Time IST
    Module 1 9:00-10:30 am 12:00-1:30 pm 6:00-7:30 pm 9:30-11:00 pm
    Module 2 11:00 am-12:30 pm 2:00-3:30 pm 8:00-9:30 pm 11:30 pm-1:00 am
    Module 3 2:00-3:30 pm 5:00-6:30 pm 11:00 pm-12:30 am 2:30-4:00 am
    Module 4 4:00-5:30 pm 7:00-8:30 pm 1:00-2:30 am 4:30-6:00 am

    MONDAY, July 13 – PST Time Zone

    9:00-10:30 am Opamp Stability and Optimization David Johns
    11:00 am-12:30 pm
    & 2:00-3:30 pm
    Low Power OpAmp Design and Biasing David Johns
    4:00-5:30 pm Circuit Noise Limitations David Johns

    TUESDAY, July 14 – PST Time Zone

    9:00 am-12:30 pm Continuous-Time Filters Boris Murmann
    2:00-3:30 pm CMOS Switched-Capacitor Circuit Design Boris Murmann
    4:00-5:30 pm Offset and 1/f Noise Reduction Techniques Boris Murmann

    WEDNESDAY, July 15 – PST Time Zone

    9:00 am-12:30 pm Gm/ID-based Design of Amplifier Circuits Boris Murmann
    2:00-5:30 pm Time Assisted Analog Design Pavan Hanumolu

    THURSDAY, July 16 – PST Time Zone

    9:00-10:30 pm Practical Techniques of Frequency Compensation Vadim Ivanov
    11:00 am-12:30 pm Voltage References Vadim Ivanov
    2:00-5:30 pm Circuit Techniques for OpAmp Speed and
    Accuracy Improvements
    Vadim Ivanov
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    Abstracts

    Advanced Analog Circuit Design
    July 13-16, 2020
    On-Line Class, PST – California Time Zone

    Opamp Stability and Optimization
    David Johns, University of Toronto

    This talk will discuss stability as it relates to small and larger circuits. Topics covered include loop-gain/poles relationship, return-ratio, blackman-impedance, pole-splitting, dealing with positive zero, and nested-miller compensation.

    Low Power OpAmp Design and Biasing
    David Johns, University of Toronto

    This talk will discuss opamp design with an emphasis on low power and biasing approaches. Topics covered include weak/strong-inversion biasing, constant-current/PTAT/constant-Gm biasing, differential, two/single-stage/multistage opamps, common-mode feedback and negative resistors.

    Circuit Noise Limitations
    David Johns, University of Toronto

    Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.

    Continuous-Time Filters
    Boris Murmann, Stanford University

    Continuous-time filters play an important role in many communication systems and at the data conversion interface, where they are required for anti-aliasing and reconstruction. This module begins by reviewing the basic s-domain filter approximations and then looks into implementations strategies. We review active RC and gm-C topologies and study their imperfections and sensitivities to nonideal effects.

    CMOS Switched-Capacitor Circuit Design
    Boris Murmann, Stanford University

    Discrete-time signals, Laplace and z-transform; Basic building blocks (opamps, switches, capacitors); Sample-and-hold circuits; SC integrators, bilinear filters and and biquads; SC amplifiers; Correlated double sampling and chopper stabilization; Nonideal effects and their correction.

    Offset and 1/f Noise Reduction Techniques
    Boris Murmann, Stanford University

    The design of precision analog interfaces in CMOS is severely impaired by offset, offset drift and 1/f noise. The material covered in this module analyzes these impairments in detail and reviews the common solutions for their remedy: chopping, autozeroing, correlated double sampling and offset stabilization. We will discuss the residual nonidealities as well as pros and cons of each technique and review typical application examples. In addition, we will survey recent advances in the state-of-the-art.

    Gm/ID-based Design of Amplifier Circuits
    Boris Murmann, Stanford University

    The majority of textbook material on CMOS analog circuit design is based on the square-law model. While this model remains useful for teaching, it has become too inaccurate for design in nano-scale CMOS. This module presents a systematic design methodology that bridges this gap using Spice-generated look-up tables. We interpret these data based on the transistor’s inversion level, employing gm/ID as a proxy and key parameter for design. With the inclusion of other width-independent figures of merit (gm/Cgg, gm/gds, etc.), this allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. Since this entire flow is driven by Spice data, we maintain close agreement between the desired specs and the circuit’s simulated performance. The presented material will detail the inner workings of this approach and illustrate it using two amplifier design examples (folded cascode and two-stage OTA).

    Time Assisted Analog Design
    Pavan K. Hanumolu, University of Illinois

    Time-based signal processing is emerging as a viable alternative to analog signal processing traditionally performed in voltage, current, or charge domains. This tutorial discusses time-based techniques to implement classical analog functions such as filtering, control and data conversion. Time-based circuits using voltage controlled ring oscillators will be presented and their design tradeoffs will be elucidated with the aid of circuit design examples.

    Practical Techniques of Frequency Compensation
    Vadim Ivanov, Texas Instruments

    Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
    We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

    Bandgap Voltage References
    Vadim Ivanov, Texas Instruments

    Discussed are error sources of the bandgap voltage references and techniques for improving their accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; single- dual and triple temperature trimming; packaging requirements; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption.

    Circuit Techniques for OpAmp Speed and Accuracy Improvement
    Vadim Ivanov, Texas Instruments

    Presented is a top down design process of the OpAmps based on the structural design methodology. We will start from selection of the gain structure, followed by the implementations of gain structures as well as gradual addition of various specific functions like PSRR/CMRR improvement, slew enhancement, overload recovery. We will consider offset improvement by trimming as well as by auto-zeroing and chopping, high-and low-voltage design specifics. Most of the circuits solutions were not published before and have been used in recent industrial ICs. Yet it is not another cookbook with analog circuit recipes. The goal of this presentation is to arm the engineers with a tool helping to invent the solution for any analog design problem and, at the same time, be reasonably sure that this solution is one of the best possible for any given process and set of constraints.

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    Wireline SERDES Transceivers

    March 22-26, 2021

    Registration deadline: February 23, 2021
    Payment deadline: March 8, 2021

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, March 22

    8:30-9:15 am Introduction to Wireline Transceivers Pavan Hanumolu
    9:15-10:00 am Transmitters (CML/VM) Pavan Hanumolu
    10:30-12:00 pm FIR Equalizers (Tx/Rx) Pavan Hanumolu
    1:30-5:00 pm Receivers (CTLE, DFE, Adaptation) Pavan Hanumolu

    TUESDAY, March 23

    8:30-12:00 pm Phase-Locked Loops Pavan Hanumolu
    1:30-3:00 pm Advanced PLLs Pavan Hanumolu
    3:30-5:00 pm Clock and Data Recovery Pavan Hanumolu

    WEDNESDAY, March 24

    8:30-10:00 am Advanced Signaling Methods Armin Tajalli
    10:30-12:00 pm Short Reach Transceiver Design Tradeoffs Armin Tajalli
    1:30-5:00 pm Tradeoffs in Design of Slicers Armin Tajalli

    THURSDAY, March 25

    8:30-10:00 am Clock and Data Recovery (ct’d) Pavan Hanumolu
    10:30-12:00 pm Baud-rate CDRs Pavan Hanumolu
    1:30-3:00 pm Introduction to PAM4 Signaling Pavan Hanumolu
    3:30-5:00 pm Trans-Impedance Amplifiers Pavan Hanumolu

    FRIDAY, March 26

    8:30-10:00 am Optical Transmitters Sam Palermo
    10:30-12:00 pm Design of ADC-Based Serial Links Sam Palermo
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    Abstracts

    Wireline SERDES Transceivers
    March 22-26, 2021
    UC Santa Cruz, California, USA

    Introduction to Wireline Transceivers
    Pavan Hanumolu, University of Illinois, USA

    An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.

    Transmitters
    Pavan Hanumolu, University of Illinois, USA

    Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.

    FIR Equalizers
    Pavan Hanumolu, University of Illinois, USA

    Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described

    Receivers
    Pavan Hanumolu, University of Illinois, USA

    Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.

    Phase-Locked Loops
    Pavan Hanumolu, University of Illinois, USA

    Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type – II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.

    Clock and Data Recovery
    Pavan Hanumolu, University of Illinois, USA

    Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.

    Advanced Signaling Methods
    Armin Tajalli, University of Utah, USA

    Moving toward data rates beyond 56 Gb/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Cordal codes, that can be used to implement very low-power and high-speed links.

    Short Reach Transceiver Design Tradeoffs
    Armin Tajalli, University of Utah, USA

    Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.

    Slicer Design
    Armin Tajalli, University of Utah, USA

    Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.

    Baud-Rate CDRs
    Pavan Hanumolu, University of Illinois, USA

    Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.

    Introduction to PAM4 signaling
    Pavan Hanumolu, University of Illinois, USA

    PAM4 signaling format will be introduced and the design challenges associated with both transmitter, receivers and equalizers will be presented.

    Trans-Impedance Amplifiers
    Pavan Hanumolu, University of Illinois, USA

    Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.

    Optical Transmitters
    Sam Palermo, Texas A&M University, USA

    This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and supercomputers. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.

    Design of ADC-Based Serial Links
    Sam Palermo, Texas A&M University, USA

    This talk provides an overview of key concepts in ADC-based serial links that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, modeling approaches, and calibration techniques.

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    Switzerland Registration Form

    Please select the course(s) you would like to attend, and fill the form at the bottom of the page.

    Special conditions

    A 15% discount applies for a combination of 2 live courses taken by the same participant. These conditions do not apply to PhD students.
    A 15% discount applies for members of a faculty who are not PhD (or Master) students.
    A special fee of CHR 1’100 is offered to PhD (or Master) students who provide an official PhD (or Master) registration certificate from their university.

    Please note that we no longer offer the exam for ECTS credits. If you want to get the credits you should be entitled to, it is up to you to apply for them at your university. We will gladly issue the necessary certificate.

    Registration to attend modules from a course held simultaneously (if any) is possible: Check here

    Nobody will be allowed to participate in a course unless their fees have been fully paid by indicated deadline.

    On receipt of your registration (or Purchase Order) a confirmation email is sent together with the invoice. Please note that from January 2025, course fees will be charged in Swiss francs (CHF). Bank coordinates where to make the wire transfer are indicated on the invoice. Other available payment methods are credit card payment through PayPal (or cash eventually on arrival).
    BEFORE signing up, please read the cancellation policy!

      JUNE 23-27, 2025

      Advanced Analog Circuit Design

      PLL Design

      Deadline for Registration: May 23, 2025
      Payment Due: June 13, 2025

      CHF 2'700.-

      CHF 2'700.-

      AUGUST 25-29, 2025

      Power Management

      Deadline for Registration: July 25, 2025
      Payment Due: August 15, 2025

      CHF 2'700.-

      SEPTEMBER 1-5, 2025

      Integrated System Design

      Deadline for Registration: August 1, 2025
      Payment Due: August 20, 2025

      CHF 2'700.-

      For PhD students Only: No exam for ECTS credits available any more.

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      BEFORE PAYING: Please submit your registration and wait for confirmation and invoice.
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      REGISTRATION INFORMATION

      Course Schedule: Courses are scheduled to begin at 8:30 am each day. There are usually four lectures (modules) per day, 1:30 hour each. Lunches are scheduled from 12:00 to 1:30 pm. There will be 30 minutes morning and afternoon coffee breaks. The restaurant offers special dishes for vegetarian and vegan people. For this and/or special dietary requirements (i.e. gluten free, etc.) please inform us on the registration form or by separate email.

      Fee Schedule: Included in the fee are lecture notes in electronic format, daily lunches and two coffee breaks. For each course, one social evening will be organized for all attendees and instructors of the course. The social event is usually held on the Wednesday evening.

      For organizational reasons, registration form should be sent before the deadline indicated above, or on each course program. Registrations are however accepted up to 7 days before the course start.

      For any question you may have about registration procedures, please contact Caroline Huber at education@mead.ch.

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      Payment of the fee should reach the course organization by the below indicated deadlines. Nobody will be allowed to participate in a course unless their fees have been fully paid by the deadline! Methods of payment can be either bank transfer, credit card payment through PayPal or by cash at the arrival. For bank transfer, bank coordinates are indicated on the invoice.

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      MEAD Education S.A.
      Ch. de la Venoge 7
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      Tel: +41-21-695-2222

      email: education@mead.ch (administrative) or valence@mead.ch (technical)

      Cancellation policy: In case of cancellation by the participant, fees will be fully refunded if a cancellation is received by the payment deadline. No refund will be issued for cancellation notices received after this date. Registration fees may be transferred to an alternative attendee or used to pay for participation in a future MEAD course. Unpaid registrants are responsible for their fees unless a cancellation is received by the deadline for payment. All reimbursement will incur a 10% fee per course.

      It can happen that a course is cancelled due to insufficient participation. In such case, MEAD takes the final decision to run the course or not on the deadline for registration day. In the case the course is cancelled, an advice is then immediately sent to the registered people. If the registered people already paid their course fees, MEAD proposes other options, such as mentioned above, as well as full reimbursement. MEAD therefore highly recommends that registrants wait until this deadline to buy their flight tickets. Hotel reservations can be made earlier, as booking cancellation is usually free of charge.

      The course schedules shown contains the best information available to MEAD at the time of the web page update. MEAD reserves the right to make changes in the schedule due to illness of the instructors or other unavoidable circumstances.


      MEAD

      MEAD Education is offering advanced engineering courses in the field of analog and mixed-signal IC design targeting the audience of electrical engineers, company managers and marketing engineers working in the semiconductor industry.

      The lecturers are leading practitioners and top experts in the area from high-technology companies and universities, who teach the most up-to-date information available at the time of the course.





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