Author Archives: Caroline

Week 1: August 26-30, 2024

Week 2: September 2-6, 2024

Registration deadline: August 7, 2024
Payment deadline: August 19, 2024

TEACHING HOURS

Monday, August 26

Tuesday, August 27

Wednesday, August 28

Thursday, August 29

Friday, August 30

Monday, September 2

Tuesday, September 3

Wednesday, September 4

Thursday, September 5

Friday, September 6

Mixed-Signal IC Design
On-Line Class, August 26 – September 6, 2024

Trade-off Between Analog and Digital – The Impact of Technology Scaling
Jan Rabaey, UC Berkeley

For over 5 decades, technology scaling has served to reduce the cost of electronic components and functionality. The same trend is still continuing today even do some of the traditional scaling strategies such as reducing supply voltages and thresholds are hitting bounds. However, there exists a perception that technology scaling primarily serves digital design, and that analog circuitry is better off with older technologies. In this lecture, we examine the trade-off between analog and digital in the nanometer era. A number of concrete examples will be used to illustrate the possible trade-offs.

Ultra Low-Power Mixed Signal Design for IoT
and Weareable Devices
Jan Rabaey, UC Berkeley

The growing importance of wireless sensor nets, ubiquitous electronics and biomedical interfaces (just to name a few) has spurred a need for mixed-signal interfaces that use only uWatts of power and hence can operate from scavenged energy. In the digital domain, sub-threshold operation at very low supply voltages is a common approach to enable ultra-low power (ULP) realization. These techniques do not translate well to the analog, mixed-signal and RF domains, where SNR and dynamic range considerations limit the scope of the supply voltage reduction. Yet, a careful balancing of the trade-off between analog and digital circuitry also allows for ULP mixed-signal to be a reality. The following three lectures will discuss various aspects of mixed-signal design for ULP wireless sensor nodes. The discussion of basic circuit design techniques will be complemented with concrete case studies.

Sensing and Data Acquisition
Advances in semiconductor techniques and MEMS have allowed sensors to substantially shrink in size and power dissipation. In fact, devices are now available to integrate multiple sensing modalities on the same die, opening the door for multi-dimensional heterogeneous data acquisition. In addition, advanced applications now require that multiple data channels (up to 1000) are acquired simultaneously. Translating all these analog inputs reliably and robustly into a digital data stream that can be used for data processing and analysis poses a formidable challenge. In this lecture various techniques for ULP data acquisition (filtering, amplification, and conversion) will be discussed. Real design examples will be used to illustrate the effectiveness of these techniques.

Computation and Communication
Making sense of all the data collected from the multitude of sensors requires some advanced processing, including artifact removal, transformation, feature extraction, classification and decision-making. While it is certainly possible to perform most of these operations in the “cloud”, latency bounds and communication limitations (which will be discussed in some detail) often require the processing to be done locally. Ultra-low energy digital processing is hence required. In this lecture, we discuss the factors limiting energy scaling in digital processing and analyze various techniques to overcome these. Special attention will be devoted to embedded machine learning and artificial intelligence techniques.

Energy Harvesting, Conversion and Storage
The ubiquity of the wireless sensor nodes require that nodes be self-sufficient from an energy perspective: they either can live on a single energy charge for their complete life cycle (e.g. smart patches), or they can harvest energy from their environment. Wireless power transmission is the most common approach to energy harvesting, but other approaches collecting energy from light or mechanical vibrations are common as well. For each of these approaches, an efficient transformation of the few amount of Joules that are available into a reliable supply voltage that can power the mixed signal and digital circuitry is of essence. This is often complicated by the fact that the energy signals are weak and need to be boosted before for instance rectification can be performed. Practical examples will help to illustrate both the challenges and the possible solutions.

Future Trends in Digital Methodolgy
Ian Rabaey, UC Berkeley

Digital logic is an essential part of every mixed-signal system-on-a-chip solution. With continued scaling of CMOS technology and the integration of more and more functionality, it has become an ever-important part. Addressing the resulting increase in complexity, caused both by technology and functionality, requires revisiting the prevailing design methodologies. While an in-depth overview in emerging trends is hard in a two-lecture sequence, we will outline some of the major trends and techniques.

Lecture 1: Evolution in digital CMOS technology and its impact on design
CMOS technology has continued scaling at a pace set by Moore’s law. However, the nature of that scaling has changed substantially over the past decade. The minimum length of a transistor has pretty much plateaued around 12-13 nm. What has continued increasing is the density (transistors/mm2). This further into an increase in performance and energy efficiency, albeit at a slower pace than before. In this presentation, we will discuss these scaling trends, how they are being accomplished, and how they may extend into the future. We further elaborate on how these developments impact the way digital circuits are designed, optimized and verified.

Lecture 2: Design methodologies for systems-on-a-chip
Digital circuits are becoming exceedingly complex. The most advanced systems-on-a-chip combine a broad range of processors (CPU, GPU), accelerators and neural processors, dedicated memory systems, networks-on-a-chip and fast input-output interfaces. Designing integrated systems of this complexity requires an evolution in design methodology, using higher levels of abstraction and more complicated building blocks. Yet, little of this is reflected in the design flows offered by the major EDA vendors today. This lecture will elaborate on how some of the emerging ideas on how design flows could evolve, including public domain components such as RISC-V, open flows and higher abstraction levels.

Noise Coupling in Mixed-Mode ICs: Mechanisms/Simulation/Measurement
Tim Schmerbeck, IBM

Survey of practical aspects of key analog and analog/digital interaction problems: Sources of noise. Methods of coupling. Effects of substrate referencing, power distribution, chip signal isolation/shielding techniques, packaging, card layout and circuit topology on noise. Analysis and modeling of particular analog and mixed signal noise problems along with experimental data results: Modeling and predicting chip/package noise prior to semi-conductor processing; Chip substrate modeling.

Noise Coupling in Mixed-Mode ICs: Design Strategy/Hardware Example
Tim Schmerbeck, IBM

Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.

Design for Electrostatic Discharge (ESD) Robustness in Silicon Integrated Circuits
Tim Schmerbeck, IBM

A general treatment of the causes and prevention of chip ESD vulnerability including the ANSI ESD models with testing & simulation methods; a comprehensive treatment of common ESD protection structures; and how to design to accommodate needed protection levels. The emphasis will be on the practical application principals for designers.

Offset and CMRR: Random and Systematic
Michiel Steyaert, KU Leuven

Random mismatch between the equally-designed transistors in a differential pair causes offset and reduction of both the CMRR and the PSRR. This phenomenon of random mismatch is discussed in detail. Its relevance is analyzed for differential pairs, current mirrors, etc. It is followed by a number of design guidelines for better matching.

Fully-Differential Amplifiers
Michiel Steyaert, KU Leuven

In mixed-mode design all circuits have to be fully differential. Therefore common-mode feedback amplifiers have to be included to ensure proper biasing and common-mode rejection. They are subject to specifications such as high frequency performance and low power consumption. All possible schematics are reviewed and compared.

Interference Effects: CMRR/PSRR
Michiel Steyaert, KU Leuven

Some EMC interference effects in integrating RF circuits are addressed and discussed. The coupling mechanism of different building blocks to the sensitive RF circuits are addressed. Design techniques for high power supply rejection ratio in basic analog building blocks are studied.

Circuit Design for EMC
Michiel Steyaert, KU Leuven

Introduction to EMC problems: EMI, EME, EMS, charge pumping. EMS design techniques on basic building blocks: principles, current mirror, input and output structures.

Time Varying Circuits in Mixed-Signal Design
Shanthi Pavan, IIT Madras

Abstract.

Modeling and Simulation, Design Methodology
Pavan K. Hanumolu, University of Illinois

Performing transistor-level simulations of mixed-mode circuits can be very time consuming. This makes performing design space exploration and circuit optimization very difficult and some times even infeasible. This tutorial discusses ways to model and simulate large mixed-mode circuits using commonly used commercial tools. Simulation examples of mixed-mode circuits such as phase-locked loops will be discussed.

Practical Techniques of Frequency Compensation
Vadim Ivanov, Texas Instruments

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

Power Management in Efficient Mixed-Signal Integrated Systems
Vadim Ivanov, Texas Instruments

Abstract.

Week 1: June 26-30, 2023

Week 2: July 3-7, 2023

Registration deadline: June 7, 2023
Payment deadline: June 16, 2023

TEACHING HOURS

Monday, June 26

Tuesday, June 27

Wednesday, June 28

Thursday, June 29

Friday, June 30

Monday, July 3

Tuesday, July 4

Wednesday, July 5

Thursday, July 6

Friday, July 7

Low-Power Analog IC Design
On-Line Class
June 26 – July 7, 2023

MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design
Christian Enz, EPFL, Switzerland

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.

Basic low-Power low-Voltage Circuit Techniques
Willy Sansen, KU Leuven, Belgium

Weak inversion and bipolar operation of MOS transistors. BiCMOS versus CMOS. Passive components and pseudo-resistive networks. Elementary building blocks operated at low supply voltage and/or low current: current mirrors, standard and special structures; differential pairs and linearization techniques; elementary voltage-gain cells, MOS- inverter amplifier. Low-voltage cascode and pseudo-cascode configurations. LP/LV current and voltage references. Translinear circuits and principle of log-domain filters.

Differential Amplifying Blocks with Positive Feedback
Willy Sansen, KU Leuven, Belgium

Practical designs are built up by means of differential pairs, current sources and two-transistor cascodes. They are analyzed in detailed followed by fully-differential voltage and current amplifiers. Positive feedback is added as well to enhance both the Gain and the Gain-Bandwidth. Design procedures are discussed in all regions of operations (from weak to strong inversion and velocity saturation).

Noise Performance of Elementary Transistor Stages
Willy Sansen, KU Leuven, Belgium

Long list of opamp configurations is discussed to show which alternative circuit tricks have been used to comply with certain specifications. Considerable design detail is presented on the symmetrical opamp and on the folded cascode. This lecture includes mainly circuit realizations in CMOS but also some in BICMOS technology.

Stability of Operational Amplifiers
Willy Sansen, KU Leuven, Belgium

Multistage operational amplifiers require compensation capacitances for stability. The conditions for stability are discussed for both two-stage and three-stage operational amplifiers. Techniques are given to avoid the positive zero and to realize minimum power consumption at the same time. Several design examples are worked out.

Systematic Design of Low-Power Operational Amplifiers
Willy Sansen, KU Leuven, Belgium

For low-power optimization, an operational amplifier can be designed for high speed and stability according to three different design procedures, all leading to the same final result. They will be discussed for a two- and three stage amplifier. The compromises with other specifications such as noise, input and output range will be discussed as well and illustrated for a number of often used configurations.

Important Opamp Configurations
Willy Sansen, KU Leuven, Belgium

Long list of opamp configurations is discussed to show which alternative circuit tricks have been used to comply with certain specifications. Considerable design detail is presented on the symmetrical opamp and on the folded cascode. This lecture includes mainly circuit realizations in CMOS but also some in BICMOS technology.

Fully-Differential Operational Amplifiers
Willy Sansen, KU Leuven, Belgium

Together with distortion, noise is the main limitation of the performance of analog circuits. It is introduced with simplified expressions for both the MOST and bipolar transistor and applied to the elementary stages with one and two transistors. Also the noise due to parasitic resistances is identified and described. Considerable attention goes to resistive and capacitive noise matching in ultra-low-noise amplifiers.

Bandgap and Current Reference Circuits
Willy Sansen, KU Leuven, Belgium

Voltage references are required in all ADC’s. Current references are required for all biasing. Bandgap references in CMOS technologies are discussed. The compromises at low power consumption are highlighted. Realizations are presented of bandgap references down to 0.8 V supply voltage.

Design of Low-power Analog Circuits using the Inversion Coefficient
Christian Enz, EPFL, Switzerland

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.

Micropower ADCs
Kofi Makinwa, TU Delft, The Netherlands

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Distortion in Elementary Transistor Circuits
Willy Sansen, KU Leuven, Belgium

For low supply voltage, a larger fraction of the total supply voltage has to be used, leading to more distortion. The several sources of nonlinear distortion are discussed for MOSTs and bipolar transistor, single-ended and differential. Also the role of feedback is examined in detail. All distortion mechanisms are analyzed in full operational amplifier configurations.

Low-Power Continuous-Time Filters
Willy Sansen, KU Leuven, Belgium

High-frequency filters are usually continuous-time type filters. They are simple in schematic and are able to handle large signals with low distortion. Moreover they need tuning circuits to be able to set the frequency and the quality factor. Most important filter schematics are reviewed and compared for high-frequency capability and power consumption.

Low-Power Frequency Reference Circuits
Taekwang Jang, ETHZ Switzerland

A reference clock frequency is required for various applications such as digital systems, sensor interfaces, data converters, wake-up controllers, and communication circuits. High precision and low noise property of the clocks are generally preferred for the stable operation of the applications. At the same time, the power overhead of the frequency reference needs to be minimized to improve the power efficiency of the system.
In this lecture, we discuss the fundamental background for frequency reference designs, including oscillation methodologies, power consumption requirements, and noise properties. Also, non-idealities such as temperature dependency, line sensitivity, and process variation are discussed. Finally, the latest designs and circuit techniques are introduced to understand the critical challenges and how to overcome those to achieve state-of-the-art performance.

Nanopower Design Techniques & Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments, USA

This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.

Week 1: November 17-21, 2025

Week 2: November 24-28, 2025

Registration deadline: November 3, 2025
Payment deadline: November 7, 2025

TEACHING HOURS

Monday, November 17

Tuesday, November 18

Wednesday, November 19

Thursday, November 20

Friday, November 21

Monday, November 24

Tuesday, November 25

Wednesday, November 26

Thursday, November 27

Friday, November 28

Cryptographic Engineering On-Line Class
November 17-28, 2025
EPFL Premises, Lausanne, Switzerland

Introduction to Block Ciphers: DES and AES
Christof Paar, Ruhr-University Bochum, Germany

We will first give a brief introduction to AES, DES and 3DES, which are the most widely used symmetric ciphers. We will then develop method for efficiently implementing both AES and 3DES in software. For AES, algorithms for both 32 bit CPUs and 8 bit smart card CPUs, will be treated. We will then introduce the bit-slicing method, an advanced and very efficient approach for fast software implementation of block ciphers. We will use DES as an example for illustrating bit-slicing.

Lightweight Block Ciphers for RFIDs
Christof Paar, Ruhr-University Bochum, Germany

For extremely resources constrained environments such as RFIDs, sensor notes or other mobile applications, it is highly desirable to have ciphers which are extremely lightweight. We will introduce optimization techniques for low-area and low-power ciphers. PRESENT, which is an extremely compact block cipher, will be discussed as a case study.

Public-Key Cryptography Algorithms and Protocols
Çetin K. Koç, UC Santa Barbara, USA

Computational requirements of RSA, Elliptic Curve Cryptography, Diffie-Hellman, ElGamal, and DSA and their ECC variants. PKC computational pyramid. PKC ALU Design. Lessons of the first RSA chip. Exponentiation and point multiplication. Addition chains. Power tree and factor method. Binary and m-ary methods. Sliding window methods. Addition-subtraction chains. Canonical encoding algorithm. The NAF algorithm and its variants. Optional: Koblitz curves and tau-adic expansions.

Integer Arithmetic Algorithms and Architectures
Çetin K. Koç, UC Santa Barbara, USA

Integer rings. Addition and multiplication. Modular addition and multiplication. Montgomery multiplication and exponentiation. Multiplicative inversion. The CIOS algorithm. Arithmetic with special primes. Solinas algorithms.

Specialized Hardware for Secret-Key Algorithms
Ingrid Verbauwhede, KU Leuven, Belgium

This lecture will introduce hardware implementation aspects of block ciphers and stream ciphers. The DES and AES algorithm will be discussed in detail. These ciphers are never used standalone but combined with modes of operation and integrated as IP blocks in larger systems. Very compact realizations and very high throughput realizations will also be discussed.

Introduction to PUFs (Physically Uncloneable Functions)
Ingrid Verbauwhede, KU Leuven, Belgium

CMOS process variations are considered a burden to IC developers since they introduce undesirable random variability between equally designed ICs. Measuring this variability can also be profitable as a physically unclonable method of silicon device identification. This can be applied to generate strong cryptographic keys which are intrinsically bound to the embedding IC instance. In this lecture, we study and compare different proposed constructions.

Finite Field Arithmetic Algorithms and Architectures
Çetin K. Koç, UC Santa Barbara, USA

Representing field elements. Polynomial and normal basis. Addition in GF(2^k). Multiplication in polynomial basis. Irreducible polynomials. Normal basis squaring. Optimal normal basis multiplication. Quadratic and sub-quadratic multiplication algorithms. Karatsuba multiplication. Recursive Karatsuba algorithm. 2-Term and 3-Term Karatsuba algorithm and generalization. Montgomery-Karatsuba formulas.

Public-Key Cryptographic Hardware and Embedded Systems
Çetin K. Koç, UC Santa Barbara, USA

Scalable dual-field arithmetic. Putting together GF(p) and GF(2^k) arithmetic. Montgomery multiplication in GF(2^k). Unified or dual-field full adder. Scalable and dual-field Montgomery multiplication. PKC on embedded software. Functional characteristics of embedded platforms. Incomplete addition. Compilers and assembler optimizations. Special curve solutions.

Introduction to Side-Channel Analysis
Marc Joye, Zama, France

Side-channel analysis is a powerful technique re-discovered by Kocher in 1996. The principle consists in monitoring some side-channel information like the running time, the power consumption or the electromagnetic radiation. Next, from the monitored data, the adversary tries to deduce the inner-workings of the algorithm and thereby to retrieve some secret information. This talk reviews the basics of side-channel analysis on various cryptographic algorithms. It is illustrated with practical examples and several side-channel attacks are mounted against several naive, unprotected implementations of cryptosystems.

Block Ciphers: Attacks & Countermeasures
Marc Joye, Zama, France

In this lecture, we will review some attacks against implementations of block ciphers. We will also present countermeasures to prevent these attacks. Focus will be on the AES block cipher.

Trusted Computing Architectures, SSL and IPSec
Pankaj Rohatgi, Cryptograpy Research, USA

Businesses, governments and individuals are increasingly reliant on complex, highly-interconnected computing platforms, mobile end-points and network centric applications to conduct much of their business. Maintaining and validating the trustworthiness of this infrastructure has therefore become critical. However, as the complexity and value of the infrastructure has increased, the number of software vulnerabilities discovered and attacks mounted against applications, platforms, end-points, identities and sensitive data within this infrastructure have grown at an even faster pace. There is a realization that given this complexity, software-only security mechanisms may not be sufficient to defend against these attacks or to evaluate the trustworthiness of a system.
Trusted computing is an effort to use trusted hardware to assist software in improving and evaluating the security for platforms, end-points, applications, identities and data. In this lecture, I will describe the Trusted Platform Module (TPM), which provides the hardware foundations for Trusted Computing and describe several ways in which the TPM could be used as a building block to improve or validate the security of platforms, end-points, applications, data and identities.

Electromagnetic Analysis and Advance Side-Channel Analysis
Pankaj Rohatgi, Cryptograpy Research, USA

This lecture will provide an introduction to the electromagnetic emanation (EM) side-channel. We will describe the various types of compromising EM emanations and the equipment needed to capture them. We will illustrate how compromising EM emanations can be captured from a variety of cryptographic devices and how multiple signals can be captured from each device. Next we will illustrate a variety of EM attacks on cryptographic implementations. Although the attack techniques are similar to power analysis, many EM attacks are not feasible using the power side channel, either because they exploit additional leakages present in EM channels or the power side-channel is inaccessible. Finally we will describe how one can design countermeasures against EM attacks.

RSA/ECC – Side Channel Attacks & Countermeasures
Marc Joye, Zama, France

Elliptic curve cryptography (ECC) shows an increasing impact in our everyday lives where the use of memory-constrained devices such as smart cards and other embedded systems is ubiquitous. Its main advantage resides in a smaller key size for a conjectured equivalent security level. In this talk, we survey different known techniques to get efficient ECC implementations that resist against a variety of implementation attacks.

RSA is the most widely used public key cryptosystem. It can be used for both encryption and signature. While the security of (black-box) RSA is well understood its secure implementation remains challenging. Basically, two classes of side-channel attacks can be distinguished: SPA-like attacks and DPA-like attacks. An SPA-like analysis is a process with a single measurement of some side-channel information; when there are several measurements handled with statistical tools, the process is referred to as a DPA-like analysis. This talk teaches how to prevent those two classes of attacks. General guidelines are provided along with concrete implementations.

Post-Quantum Cryptography Algorithms
Francisco Rodrìguez-Henrìquez, Cryptography Research Centre of the Technology Innovation Institute at Abu Dhabi, UAE

As of today, most cryptographic systems deployed in the real world use asymmetric primitives that rely on the hardness of integer factorization (most notably RSA public-key encryption and signatures), or the (elliptic-curve) discrete-logarithm problem. While a sensible choice of parameters for these schemes are believed to resist attacks launched from classical computers, it is known since Shor’s seminal 1994 paper, that a large universal quantum computer will be able to solve both factoring and discrete logarithms in polynomial time. Fortunately, when sufficiently large quantum computer become a reality, this will not imply the end of efficient public-key cryptography. There exist various approaches for constructing public-key encryption or key-encapsulation mechanisms (KEMs) and signatures that — as far as we know — can resist attacks coming from large universal quantum computers.
In this lecture we present an introduction to the most important techniques for achieving a secure and efficient implementation of so-called post-quantum cryptography, the anticipated next generation of asymmetric cryptography. Concretely, we will study five main approaches to construct such post-quantum cryptography, namely, Lattice-based Cryptography, Code-based Cryptography, Multivariate Cryptography, Hash-based Cryptography, Isogeny-based Cryptography.

Post-Quantum Cryptography Implementation
Francisco Rodrìguez-Henrìquez, Cryptography Research Centre of the Technology Innovation Institute at Abu Dhabi, UAE

In this class we present an introduction to the most important techniques for achieving a secure and efficient implementation of so-called post-quantum cryptography, the anticipated next generation of asymmetric cryptography. Concretely, we will revise the algorithms and their best software implementation practices.

Fully Homomorphic Encryption
Marc Joye, Zama, France

Fully homomorphic encryption (FHE) allows computing over encrypted data. In this lecture, we will cover some advanced topics in FHE. In particular, we will cover bootstrapping of ciphertexts and its extension to programmable bootstrapping. The general case of multivariate functions over encrypted data will also be dealt with. Applications to the private evaluation of neural networks will be discussed.

Random Number Generators for Cryptographic Applications
Werner Schindler, BSI Bund, Germany

Many cryptographic mechanisms require random numbers, e.g. as challenges, session keys or signature parameters. Inappropriate random number generators may weaken principally strong cryptographic mechanisms considerably. Requirements are formulated that appropriate random number generators should fulfill and concrete examples are discussed. Relevant differences between deterministic and the non-deterministic random number generators are worked out.

Evaluation Criteria for Non-Deterministic Random Number Generator
Werner Schindler, BSI Bund, Germany

In this lecture, I will investigate in more details the problem of physical security evaluations against side-channel attacks, with applications to implortant classes of countermeasures such as masking. In a first step, I will descibe formal approaches to quantify the information leakages and put forward their potential shortcomings. Next, I will use case studies to illustrate that one can gain good intuition about the security of certain implementation based on simple heuristic formulas.

Random Number Generator Design Constraints and Challenges
Viktor Fischer, Université de Saint Etienne, France

In this lecture, we will first analyze the main characteristics of random number generators (RNGs): quality related issues such as sources of randomness, entropy extraction principles, post-processing, output bit-rate and its stability; security related issues such as existence of a mathematical model, inner testability and robustness against attacks; design related issues such as resource usage, power consumption, feasibility in logic devices and design automation. Next, we will critically analyze and compare the main existing RNG principles. Based on this analysis, we will point out pitfalls that can exist in a practical RNG design and challenges that are usually faced when designing secure RNGs according to recommendations AIS 20/AIS 31.

July 13-17, 2020

Registration deadline: June 17, 2020
Payment deadline: June 27, 2020

TEACHING HOURS

MONDAY, July 13 – PST Time Zone

TUESDAY, July 14 – PST Time Zone

WEDNESDAY, July 15 – PST Time Zone

THURSDAY, July 16 – PST Time Zone

FRIDAY, July 17 – PST Time Zone

Wireline SERDES Transceivers
July 13-17, 2020
On-Line Class, PST – California Time Zone

Introduction to Wireline Transceivers
Pavan Hanumolu, University of Illinois, USA

An introduction to the applications, specifications and architectures of today’s high-speed wireline transceivers. An overview of application requirements and trends, along with channel impairments, clocking specifications, and modulation formats will be reviewed.

Transmitters
Pavan Hanumolu, University of Illinois, USA

Transmitter circuit design for high-speed electrical links, including termination, current- and voltage-mode drivers will be presented. Practical techniques for biasing, ac-coupling, and termination will be discussed.

FIR Equalizers
Pavan Hanumolu, University of Illinois, USA

Finite impulse response (FIR) equalization circuits will be studied. Circuits implementing them at both transmitter (both CM and VM) and receiver will be described

Receivers
Pavan Hanumolu, University of Illinois, USA

Receiver termination, amplification, and equalization circuits will be studied, including linear and decision-feedback equalization. Equalization in continuous- and discrete-time, using FIR and IIR filters, and speculative (look-ahead) techniques will be covered. Adaptation of equalizer parameters using LMS and zero-forcing criteria will be presented.

Phase-Locked Loops
Pavan Hanumolu, University of Illinois, USA

Clock generation techniques for wireline transceivers using phase locked loops (PLLs) will be presented. Starting with the description of fundamentals of type – I and type – II PLLs, we discuss the circuit implementation details of analog, digital, and hybrid PLL architectures. Advanced PLLs using injection locking will be presented.

Clock and Data Recovery
Pavan Hanumolu, University of Illinois, USA

Clock and data recovery (CDR) is a key function in all serial link applications. This tutorial elucidates the design challenges and trade-offs involved in the design of CDRs. The jitter performance metrics such as jitter generation, jitter transfer, and jitter tolerance are related to digital CDR parameters and design guidelines will be provided. Circuit implementation details will be presented.

Advanced Signaling Methods
Armin Tajalli, University of Utah, USA

Moving toward data rates beyond 56 Gb/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Chordal codes, that can be used to implement very low-power and high-speed links.

Short Reach Transceiver Design Tradeoffs
Armin Tajalli, University of Utah, USA

Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.

Tradeoffs in Design of Slicers
Armin Tajalli, University of Utah, USA

Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.

Discrete-Time Front-End Design
Armin Tajalli, University of Utah, USA

Design of high-speed front-end circuits, especially for receivers, is becoming more and more challenging. The need for more complex equalization schemes highlights the importance of designing very high-speed continuous-time and discrete-time circuits. The main focus of this lecture will be on circuit topologies that modern receivers use to extend their bandwidth and functionality. The lecture will start with a short introduction on a novel design algorithm to maximize the speed and energy-efficiency of analog circuits, followed by introducing several new circuit topologies for implementing DFEs.

Baud-Rate CDRs
Pavan Hanumolu, University of Illinois, USA

Baud-rate CDR architectures using various timing functions will be described. Circuit implementation details will be presented.

Introduction to PAM4 signaling
Pavan Hanumolu, University of Illinois, USA

PAM4 signaling format will be introduced and the design challenges associated with both transmitter, receivers and equalizers will be presented.

Trans-Impedance Amplifiers
Pavan Hanumolu, University of Illinois, USA

Transimpedance amplifiers (TIA) used in high-speed optical links will be described. Fundamental noise versus bandwidth tradeoffs will be presented and techniques to overcome them will be provided.

Optical Transmitters
Sam Palermo, Texas A&M University, USA

This talk covers circuit design techniques relevant to high-speed optical transmitters used in datacenters and supercomputers. Transmitter circuits for different optical sources, including laser drivers for edge-emitting and vertical-cavity surface emitting lasers and external modulator drivers for Mach-Zehnder, electroabsorption, and ring resonator modulators are presented.

Design of ADC-Based Serial Links
Sam Palermo, Texas A&M University, USA

This talk provides an overview of key concepts in ADC-based serial links that support operation over high-loss channels. Topics covered include high-speed ADC topologies, digital equalizers, benefits of partial analog equalization, modeling approaches, and calibration techniques.