Week 1: March 12-15, 2024

Week 2: March 18-22, 2024

Registration deadline: February 23, 2024
Payment deadline: March 1, 2024

TEACHING HOURS

Tuesday, March 12

Wednesday, March 13

Thursday, March 14

Friday, March 15

Monday, March 18

Tuesday, March 19

Wednesday, March 20

Thursday, March 21

Friday, March 22

Hardware-Efficient Edge AI
On-Line Class
March 12-22, 2024

Course Abstract

Artificial intelligence workloads become more and more important for intelligent edge and extreme-edge devices, a trend also known as “tinyML”. Yet, these workloads come with significant computational complexity, making their execution until recently only feasible on power-hungry server or GPU platforms. Recently a surge of techniques at the algorithmic, hardware architecture and circuit domain are now also creating breakthroughs to enable ML workloads in real-time embedded devices at the edge and extreme edge under low energy and latency budget. Such system optimization, however, does require thorough knowledge and cross-layer optimization across all these fields, all the way from application and algorithm, over compilers and schedulers, to system design, macro-architecture design and circuit design. In this course, we will go over all these aspects of machine learning at the edge, with especially a deeper dive into hardware optimization opportunities. Enough time is also foreseen to discuss practical case studies and end-to-end-optimizations.

ML Applications, Scenario’s and Constraints for the Edge
Marian Verhelst, KU Leuven, Belgium

– Overview of applications
– Cloud vs Edge vs tinyML (extreme edge)
– Inference vs learning vs federated learning
– Application constraints and scenario’s
– Flavors of ML and AI (types of models)

ML Algorithms and Resulting Challenges
Marian Verhelst, KU Leuven, Belgium

Computational consequences and HW requirements for the EDGE of:
– Probabilistic models
– decision trees
– SVM’s
– NN’s (deep and non-deep; layer types, …)
– NN training
– Hyperdim computing?
Challenges and requirements for efficient AI at the edge.

Neural Network Compression for the Edge
Tijmen Blankevoort, Meta, The Netherlands

– Take any network, how can we make it smaller structurally?
– Neural Network Pruning
– Structured Compression
– Neural Architecture Search as a compression method.

Neural Network Quantization for the Edge
Tijmen Blankevoort, Meta, The Netherlands

– Quantization Introduction and Simulation
– Quantization-aware training
– Post-training quantization techniques
– Mixed Precision.

Specializing Processors for ML
Luca Benini, Università di Bologna, Italy/ETHZ, Switzerland

– Classical instruction set architectures (ISAs) limitations for ML
– ISA Extensions for ML
– Micro-architecture of ML-specialized cores
– PPA (power performance area) optimization and implementation techniques.

From Single to Multi-Core Low-Power SoCs for ML
Luca Benini, Università di Bologna, Italy/ETHZ, Switzerland

– Single-core ML SoCs – architecture, implementation, PPA analysis
– Multi-core ML SoCs – architecture, implementation, PPA analysis
– Integration of cores and Hardwired ML accelerators
– Memory hierarchy: challenges and solutions.

Concepts Towards ML Acceleration
Marian Verhelst, KU Leuven, Belgium

– ML models / CNN / DNN recap formalization; GeMM
– GeMM on traditional CPU / GPU
– Energy/latency losses and opportunities
– Concepts towards more efficient ML acceleration on single core/single layer
– Parallelization (spatial unrolling optimization)
– Stationarity (temporal unrolling optimization)
– Extending spatial and temporal unrolling to higher levels.

Exploiting Quantization and Sparsity at the HW Level
Marian Verhelst, KU Leuven, Belgium

– Concepts towards more efficient AI acceleration on single core/single layer (ctu)
– Sparse workloads
– Quantization – analog domain
[Optional: – Concepts towards more efficient AI acceleration on multi-core/multi-layer]. 

Analog/Mixed-Signal Acceleration
Naveen Verma, Princeton University, USA

– Review of key ops to accelerate (MACs) and potential energy savings through analog
– Overview of Approaches for MACs
• Electronic (current, voltage, charge summing)
• Optical
– Overheads and limitations
• Memory accessing -> motivates in-memory computing
• Data conversion
• Technology integration with digital engines/memory
– Fundamental tradeoffs
• Energy/throughput vs SNR
– In-memory computing
• Different memory techs and approaches.

Architectural Integration of Emerging Compute Models and Technologies
Naveen Verma, Princeton University, USA

– Dataflow bottlenecks (weight/state loading)
– Structured memory accessing and benefits of emerging memory
– Co-design with trainers.

Tools: Accelerator Code Generation
Tobias Grosser, University of Cambridge, UK

Abstract.

Tools: Accelerator Code Generation
Tobias Grosser, University of Cambridge, UK

Abstract.

Emerging ML Paradigms: Neuro-Inspired Computing
Jan Rabaey, UC Berkeley, USA

Lessons from the brain and what it means for:
– ML hardware,
– Neuromorphic,
– Hyper-dimensional, etc.

Emerging ML Paradigms: Towards Cognitive Systems
Jan Rabaey, UC Berkeley, USA

– Autonomous sensor-control-actuation
– Model versus data driven
– Reinforcement learning
– Symbolic reasoning
– Probabilistic learning, graphs

Efficient Execution of Approximated AI Algorithms on Heterogeneous Edge AI Systems
David Atienza, EPFL, Switzerland

i. Major challenges in designing energy-efficient edge AI architectures due to the complexity of AI/CNN.
ii. Design options to reduce complexity (pruning, quantization, etc.) and benefits of operating edge AI architectures at sub-nominal conditions.
iii. New architectural design methodologies for edge AI systems, called Embedded Ensemble CNNs (E2CNNs) to conceive pruned CNNs and AI implementations with improved robustness against memory errors in pruned/quantized single-instance ML/CNNs.
iv. Experimental evaluation of compression methods and design space exploration to produce an ensemble of CNNs for edge AI devices with the same memory requirements as the original architectures but improved error robustness (in different types of memories) for sub-threshold operation.

Application-Driven System Design and Optimization flow of Edge AI Use Cases in Industrial and Medical Domains
David Atienza, EPFL, Switzerland

i. Overview of major key challenges in different industrial case studies for AI/ML systems (computation vs communication and other trade-offs to consider particularly for medical applications in the context of Big Data healthcare).
ii. Different design option for AI/ML hardware systems using centralized vs. federated approaches on edge AI systems.
iii. Mapping options for ULP multi-core embedded systems with neural network accelerators for energy-scalable software layers based on target applications.
iv. Examples of next-generation of smart wearable devices in the healthcare context
v. Examples of industrial edge AI systems for home automation.

Practical Case Studies: “Energy Efficient ML Applications for Metaverse”
Huichu Liu, Meta, USA

– Overview of AR/VR system features and energy constraints
– Breakdown different applications running on AR/VR HW and its related ML algorithms
– HW techniques to enable energy efficient NN execution
– HW-SW techniques to enable efficient NN mapping
– Algorithm techniques for practical applications
– Future applications/challenges/research directions

Cross-Layer Optimization
Marian Verhelst, KU Leuven, Belgium

– Need for optimization across the stack cross layer design space exploration
– Tools flows for cross layer optimization
– Final Q&A and adjourn

Week 1: January 12-16, 2026

Week 2: January 19-23, 2026

Registration deadline: January 5, 2026
Payment deadline: January 9, 2026

TEACHING HOURS

Monday, January 12

Tuesday, January 13

Wednesday, January 14

Thursday, January 15

Friday, January 16

Monday, January 19

Tuesday, January 20

Wednesday, January 21

Thursday, January 22

Friday, January 23

Power Management
On-Line Class
January 19-23, 2026

Fundamentals of SC Converters and Topologies
Filip Tavernier, KU Leuven, Belgium

This lecture will discuss the working principle, fundamental characteristics, and taxonomy of switched-capacitor DC-DC converters. Three analysis techniques will be introduced that can help to understand and design SC converters: Charge Flow Analysis, Charge Balance Analysis, and Branch Analysis. These techniques will be applied to gain insight into the most commonly used SC converter topologies.

Analysis and Modeling of SC Converters
Filip Tavernier, KU Leuven, Belgium

This lecture will discuss the output impedance model and give an overview of the extrinsic losses of SC converters. Next, the converter topology selection and its optimization for minimal losses will be discussed, both for single-topology and multi-topology SC converters. Finally, multi-phase interleaving will be discussed as a technique to reduce switching noise.

Power Stages
Bernhard Wicht, Leibniz University Hanover, Germany

After a brief overview of various types of power transistors, this lecture covers power switch sizing along with associated parasitics and isolation methods. Consequently, the influence on switching behavior and losses is investigated. Fundamental circuits include switch-stacking and back-to-back configurations.

Gate Drivers and Protection
Bernhard Wicht, Leibniz University Hanover, Germany

This lecture is dedicated to the design of low-side and high-side gate drivers as well as of fast and robust level shifters. It includes optimization regarding delay, power dissipation and area. Protection circuits and methods against over-voltage, over-current, short circuits, etc. are discussed as well as current sensing circuits.

GaN Drivers and Circuit Design
Bernhard Wicht, Leibniz University Hanover, Germany

Gallium Nitride (GaN) as a new semiconductor material enables compact and efficient power electronics in a wide range of applications. With significantly lower gate as well as output charge, GaN offers superior switching performance at frequencies in the MHz domain, much higher compared to Silicon power devices. This talk covers system and circuit approaches for GaN power stages and gate drivers and discusses how monolithic integration advances the overall system objectives.

Protection and Sensing
Bernhard Wicht, Leibniz University Hanover

Power management designs must deal with high voltages and large currents that require protection of the connected loads and power stage from damage. They have to ensure operation within the maximum ratings. This lecture emphasizes fundamental protection functions like over-voltage, over-current, thermal protection, short circuits, and open loads. During regular operation, various conditions and quantities must be controlled and require sensing circuits, such as zero-voltage crossing detection. As an essential topic, current sensing circuits are discussed in detail.

Fundamentals of Inductive DC-DC Converters
Bernhard Wicht, Leibniz University Hanover, Germany

With the increasing need for efficient power supplies, inductor-based switched mode power supplies are being widely used. They provide excellent power efficiency at the expense of increased complexity and noise. This talk gives a general introduction into voltage and current mode control for inductive DC-DC converters including control loop design and basic circuit blocks. A particular focus is on fast switching converters with small passive components that enable a high level of integration.

Hybrid Converters
Bernhard Wicht, Leibniz University Hanover, Germany

Hybrid DC-DC converters pursue an extremely promising approach by combining capacitor-based and inductive concepts in a single converter structure. Resonant operation allows for switching frequencies in the multi-Megahertz range at significantly reduced dynamic losses. Better utilization of passives enables fully integrated converter designs, which include all passive components either on-chip or by co-integration in the same package. This lecture explores solutions on system and circuit level and presents examples, in particular, for portable applications and wearables.

Fundamentals of Linear Regulators
Pavan Hanumolu, University of Illinois, USA

Design, analysis, and practical circuit implementation of low dropout regulators (LDOs) are presented. We begin with a review of traditional LDO regulator topologies and evaluate their key performance metrics such as dropout voltage, power supply rejection ratio, load and line regulation accuracy, settling time in the presence of load step, current efficiency, and stability. Following this, we describe alternate LDO architectures and illustrate how one can tradeoff some of the performance metrics.

LED Drivers Design
Pavan Hanumolu, University of Illinois, USA

LED-based lighting is emerging as a preferred choice for both home/commercial lighting and in portable applications such as camera flash, display backlights in mobile phones, tablets, laptops. This tutorial focuses on design techniques for LED drivers geared specifically to battery-driven portable applications. Efficient DC-DC switching converter architectures to implement such LED drivers along with design examples will be presented.

Digitally Controlled DC-DC Converters
Pavan Hanumolu, University of Illinois, USA

Digital control techniques offer flexibility, reduced sensitivity to component variations, and reconfigurability of DC-DC converters compared to their analog counterparts. The circuit- and system-level tradeoffs involved in the design of digitally-controlled switching converters will be discussed. Circuit techniques to implement analog-to-digital converters and digital PWM controllers will be presented.

Time-Based Control of DC-DC Converters
Pavan Hanumolu, University of Illinois, USA

Time-based control techniques for the design of high switching frequency buck converters are presented. We first describe how to use time as the processing variable (as opposed to voltage, current, or charge) and then discuss the implementation time-based controller that operates with CMOS-level digital-like signals but without adding any quantization error. Finally, the circuit implementation details of the time-based buck converter are described.

Interference and PSRR
Michiel Steyaert, KU Leuven, Belgium

Some EMC interference effects in integrating RF circuits are addressed and discussed. The coupling mechanism of different building blocks to the sensitive RF circuits are addressed. Design techniques for high power supply rejection ratio in basic analog building blocks are studied.

Bandgap Voltage References
Michiel Steyaert, KU Leuven, Belgium

The lectures start with an introduction on merits of MOSTs versus bipolar transistors in the different positions of an operational amplifier. Then the design procedures are given for optimal op-amp design by means of the pole-zero position and Bode diagrams. A second-order Miller op-amp is discussed in great detail followed by a design procedure for third-order nested Miller op-amps. All of them are optimized towards high GBW, low noise and minimum power consumption. Finally a considerable number of other configurations are discussed and compared, among which a few very-low-voltage fully-differential operational amplifiers, involving internal common-mode feedback.

DC-DC: From Discrete towards Fully CMOS Integrated
Michiel Steyaert, KU Leuven, Belgium

Trends and techniques towards fully integrated CMOS DC-DC converters is studied. Both inductive and capacitive DC-DC converters are analyzed. The different required on chip components such as inductors are discussed. Different control loop techniques are presented in order to achieve high integrated density and meanwhile achieving low ripple requirements. Many designed cases, both boost and buck are analyzed and compared with classical LDO regulators.

Practical Techniques of Frequency Compensation
Vadim Ivanov, Texas Instruments, USA

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

Design of the LDO’s with Instant Load Regulation and Unconditional Stability
Vadim Ivanov, Texas Instruments, USA

Discussed is a new class of LDO’s: any load stable, with instant transient response, large power supply rejection and low noise. Examples include the embedded in SoC LDOs for the SRAM unit (5 ns reaction time on the load steps), LDO for radio transmitter (shaping the required noise vs. frequency curve) and LDO for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process.

Circuit Techniques for Integrated Switching Regulators
Vadim Ivanov, Texas Instruments, USA

Power switches: static and dynamic power loss, switch sizing, wire bonds and their inductance, parasitic vertical PNP and lateral NPN structures, substrate noise, signal grounding and isolation of the control circuitry. Switch Control: Low and high-side gate drivers, use of the bootstrap capacitors with charge regeneration, transfer of the control signal to the high-side. Low and high-side synchronous rectifiers: comparator design, minimization of delays, elimination of shoot-through currents. Feedback and frequency compensation: continuous and discontinuous operation, current and voltage mode; inductor current sensing with and without external elements; oscillator and PWM circuits; error amplifier.

Nanopower Design Techniques and Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments, USA

This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.