August 29 – September 2, 2022

Registration deadline: July 15, 2022
Payment deadline: August 19, 2022

Download One-Page Schedule Here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, August 29

TUESDAY, August 30

WEDNESDAY, August 31

THURSDAY, September 1

FRIDAY, September 2

Low-Power Analog IC Design
August 29 – September 2, 2022
EPFL Premises, Lausanne, Switzerland

MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design
Christian Enz, EPFL

Evolution of CMOS technologies: process scaling, low-voltage constraint. Basic long-channel static theory. Short- and narrow-channel effects. Quasi-static dynamic model. Thermal and flicker noise model. Parameter extraction. The EKV model and its use for LV and LP analog circuit design.

Basic low-Power low-Voltage Circuit Techniques
Willy Sansen, KU Leuven

Weak inversion and bipolar operation of MOS transistors. BiCMOS versus CMOS. Passive components and pseudo-resistive networks. Elementary building blocks operated at low supply voltage and/or low current: current mirrors, standard and special structures; differential pairs and linearization techniques; elementary voltage-gain cells, MOS- inverter amplifier. Low-voltage cascode and pseudo-cascode configurations. LP/LV current and voltage references. Translinear circuits and principle of log-domain filters.

Differential Amplifying Blocks with Positive Feedback
Willy Sansen, KU Leuven

Practical designs are built up by means of differential pairs, current sources and two-transistor cascodes. They are analyzed in detailed followed by fully-differential voltage and current amplifiers. Positive feedback is added as well to enhance both the Gain and the Gain-Bandwidth. Design procedures are discussed in all regions of operations (from weak to strong inversion and velocity saturation).

Noise Performance of Elementary Transistor Stages
Willy Sansen, KU Leuven

Long list of opamp configurations is discussed to show which alternative circuit tricks have been used to comply with certain specifications. Considerable design detail is presented on the symmetrical opamp and on the folded cascode. This lecture includes mainly circuit realizations in CMOS but also some in BICMOS technology.

Stability of Operational Amplifiers
Willy Sansen, KU Leuven

Multistage operational amplifiers require compensation capacitances for stability. The conditions for stability are discussed for both two-stage and three-stage operational amplifiers. Techniques are given to avoid the positive zero and to realize minimum power consumption at the same time. Several design examples are worked out.

Systematic Design of Low-Power Operational Amplifiers
Willy Sansen, KU Leuven

For low-power optimization, an operational amplifier can be designed for high speed and stability according to three different design procedures, all leading to the same final result. They will be discussed for a two- and three stage amplifier. The compromises with other specifications such as noise, input and output range will be discussed as well and illustrated for a number of often used configurations.

Important Opamp Configurations
Willy Sansen, KU Leuven

Long list of opamp configurations is discussed to show which alternative circuit tricks have been used to comply with certain specifications. Considerable design detail is presented on the symmetrical opamp and on the folded cascode. This lecture includes mainly circuit realizations in CMOS but also some in BICMOS technology.

Fully-Differential Operational Amplifiers
Willy Sansen, KU Leuven

Together with distortion, noise is the main limitation of the performance of analog circuits. It is introduced with simplified expressions for both the MOST and bipolar transistor and applied to the elementary stages with one and two transistors. Also the noise due to parasitic resistances is identified and described. Considerable attention goes to resistive and capacitive noise matching in ultra-low-noise amplifiers.

Bandgap and Current Reference Circuits
Willy Sansen, KU Leuven

Voltage references are required in all ADC’s. Current references are required for all biasing. Bandgap references in CMOS technologies are discussed. The compromises at low power consumption are highlighted. Realizations are presented of bandgap references down to 0.8 V supply voltage.

Design of Low-power Analog Circuits using the Inversion Coefficient
Christian Enz, EPFL

The supply voltage of CMOS chips has constantly been scaled down in the last years to reach now the sub-1V region. This supply voltage reduction is mainly driven on one hand by the technology constraints to maintain a reasonable electric field within the MOS device to avoid high-field effects and on the other hand by the needs of digital circuits to reduce the dynamic power consumption. Analog circuits unfortunately don’t take any advantage of this voltage down-scaling since almost all their performances are degraded and some basic circuits would even stop operating correctly. We will discuss the main challenges faced when designing analog circuits for ultra-low voltage (ULV) operation. We will first present the fundamental limits set by ULV, together with the technology limitations (such as matching) for analog circuits. We will then have a closer look at the MOS transistor operation with a particular focus on weak inversion, the Gm/ID characteristic and the inversion coefficient design approach. We then will review several basic building blocks capable of operating at ULV, including both continuous-time and sampled-data circuits. Finally we will investigate the potential of designing RF circuits in ULV taking advantage of ultra-deep submicron processes and give some design examples.

Distortion in Elementary Transistor Circuits
Willy Sansen, KU Leuven

For low supply voltage, a larger fraction of the total supply voltage has to be used, leading to more distortion. The several sources of nonlinear distortion are discussed for MOSTs and bipolar transistor, single-ended and differential. Also the role of feedback is examined in detail. All distortion mechanisms are analyzed in full operational amplifier configurations.

Low-Power Continuous-Time Filters
Willy Sansen, KU Leuven

High-frequency filters are usually continuous-time type filters. They are simple in schematic and are able to handle large signals with low distortion. Moreover they need tuning circuits to be able to set the frequency and the quality factor. Most important filter schematics are reviewed and compared for high-frequency capability and power consumption.

Practical Techniques of Frequency Compensation
Vadim Ivanov, Texas Instruments

Every analog IC comprises multiple feedback loops. Interaction between these loops makes frequency compensation of such system non-trivial task, unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which may cause conditional stability and complicate compensation.
We will consider system structure design for stability, needed for it elementary circuit cells additional to the textbook techniques, as well as ways to achieve unconditional system stability when component parameters vary, and when load and signal source impedance is not well defined. Examples include LDOs stable with any load capacitance, transconductors with wide (few volts) input voltage range, and multistage operational amplifiers.

Nanopower Design Techniques & Efficient Energy Harvesting
Vadim Ivanov, Texas Instruments

This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and battery chargers with maximum power point tracking and battery protection.

Micropower ADCs
Kofi Makinwa, TU Delft

With the current trend towards increasingly autonomous systems, micropower ADCs have become critical components. In this presentation, the basic principles of micropower SAR and sigma-delta ADCs will be discussed. It will also be shown how these two proven techniques can be combined to realize high resolution micropower ADCs.

Matching of MOS Transistors in Deep-Submicron
Marcel Pelgrom, NXP Semiconductors

Orders of magnitude. Offset: electrical, technological and timing aspects. Random matching: general description, application to MOS. Deep submicron CMOS matching considerations. Modeling and simulation of MOS transistor mismatch. Design examples. Packaging effects.

June 23-27, 2025

Registration deadline: May 23, 2025
Payment deadline: June 17, 2025

Dowload one-page schedule here

Course material will be distributed only if fees have been paid by the deadline for payment.

MONDAY, June 23

TUESDAY, June 24

WEDNESDAY, June 25

THURSDAY, June 26

FRIDAY, June 27

PLL Design
June 23-27, 2025
EPFL Premises, Lausanne, Switzerland

Fundamentals of Analog PLLs
Michiel Steyaert, KU Leuven, Belgium

Basic definitions and concepts of phase locked loop topologies. Frequency behaviour, stability and settling of PLL topologies. Introduction of analog, digital and fractional N synthesizers. Introduction to Phase noise and jitter.

Interference Effects in PLLs
Michiel Steyaert, KU Leuven, Belgium

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.

Spiral Inductor Interference, Deadzone and Phase Noise
Michiel Steyaert, KU Leuven, Belgium

Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.

VCO Design – Jitter and Phase Noise in PLLs
Ali Hajimiri, Caltech, USA

We start this lecture with an overview of the VCO noise concepts and some of the classical work in this area. We elucidate some of the basic properties of oscillator phase noise through several thought experiments. Then we go through a step-by-step development of a time-varying noise model for oscillators and discuss the evolution of noise in an oscillator from its physical sources to frequency and amplitude fluctuations. In this process, we see how low frequency noise sources affect the oscillator behavior and discuss the impact of time-varying and correlated noise source. In the second part of the lecture, we discuss how the new design insights obtained from our model leads to novel VCO topologies that overcome some of their basic challenges and limitations. We discuss additional trade-offs in VCOs and apply them in the context of several practical design examples for a broad range of frequencies and applications. Finally, we focus our attention to the noise process in phase-locked loops and analyze it using a parallel time- and frequency-domain analysis of noise in PLLs.

PLL Analysis and Modeling
Sam Palermo, Texas A&M University, USA

This talk covers modeling techniques for analog and digital PLLs. This includes linear continuous-time (s-domain) and discrete-time (z-domain) models and non-linear time-domain models that allow for optimization of system bandwidth, stability, and noise performance.

PLL Building Blocks
Sam Palermo, Texas A&M University, USA

This talk covers circuit design techniques for the main building blocks, excluding the VCO, used in analog and digital PLLs. This includes phase detectors, time-to-digital converters, analog and digital loop filters, and high-speed dividers.

Analog Fractional-N PLLs for Frequency Synthesis
Ian Galton, UC San Diego, USA

This lecture explains the extension of integer-N PLLs to fractional-N PLLs for both fine tuning resolution and in-loop VCO modulation. It presents an overview of modulus quantization noise shaping techniques, tradeoffs associated with quantization noise shaping order and PLL loop bandwidth, non-ideal effects of particular concern in fractional-N PLLs such as charge pump nonlinearities and data-dependent multi-modulus divider delays, techniques for increasing loop bandwidth, simulation techniques, and case studies of example circuits and applications.

All-Digital PLL Architecture and Implementation
Bogdan Staszewski, UCD, Ireland

The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic. This lecture presents a system level view of the ADPLL:

1. Principles of phase-domain frequency synthesis 2. ADPLL closed-loop behavior 3. Direct frequency modulation of ADPLL 4. Alternative TX architectures using ADPLL and PA regulator 5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design.

Time-to-Digital Converter (TDC)
Bogdan Staszewski, UCD, Ireland

A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay (about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level implementation issues.

FDC-Based Digital PLLs
Ian Galton, UC San Diego, USA

While both analog and digital fractional-N PLLs introduce quantization error, the majority of digital PLLs developed to date introduce quantization error with higher power or higher spurious tones than comparable analog PLLs. Digital PLLs based on second-order delta-sigma frequency-to-digital conversion address this problem in that their quantization noise ideally is equivalent to that of analog PLLs with second-order delta-sigma modulation. This talk describes the underlying theory and practical implementation of digital PLLs based on frequency-to-digital conversion and illustrates the presented concepts with IC implementation details and measured results.

Digitally-Controlled Oscillator (DCO)
Bogdan Staszewski, UCD, Ireland

A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but with a significant difference in one of the components: instead of continuously tuned varactor (variable capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed in either high or low capacitive state. The composite varactor performs digital-to-capacitance conversion. This lecture presents a circuit system level view of DCO.

Clock Generation and Distribution in Wireline Systems
Sam Palermo, Texas A&M University, USA

This talk covers clock generation and distribution schemes commonly used in wireline systems. Topics include system jitter budgeting, PLL jitter modeling, clock distribution circuitry, and multi-phase clock generation and calibration schemes.

PLL-Based Clock and Data Recovery Systems
Sam Palermo, Texas A&M University, USA

This talk covers PLL-based clock and data recovery systems for wireline communication applications. Topics include basic operation, performance metrics, CDR architectures, phase and frequency detectors, and system design considerations.