Techniques for Handling Noise and Variability in Analog Circuits

    January 25-29, 2021

    Registration deadline: December 19, 2020
    Payment deadline: January 11, 2021

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, January 25

    8:30-12:00 pm Random Mismatch Origins Marcel Pelgrom
    1:30-5:00 pm Analyzing Mismatch and Yield in Analog Circuits Marcel Pelgrom

    TUESDAY, January 26

    8:30-12:00 pm Layout Strategies to Reduce Offset Marcel Pelgrom
    1:30-3:00 pm Offset, CMRR and PSRR Willy Sansen
    3:30-5:00 pm Variability in Bandgaps Willy Sansen

    WEDNESDAY, January 27

    8:30-12:00 pm Fundamentals of Noise in Electronic Devices Christian Enz
    1:30-3:00 pm Noise Cancellation Techniques Willy Sansen
    3:30-5:00 pm Noise Sampling in Switched Capacitor Filters Willy Sansen

    THURSDAY, January 28

    8:30-12:00 pm
    & 1:30-3:00 pm
    Noise Analysis in Continuous-Time and Sampled-Data Circuits Christian Enz
    3:30-5:00 pm Dynamic Offset-Cancellation Techniques Kofi Makinwa

    FRIDAY, January 29

    8:30-10:00 am  Dynamic Offset-Cancellation Techniques Kofi Makinwa
    10:30-12:00 pm
    & 1:30-3:00 pm
    Dynamic Element Matching Techniques Kofi Makinwa
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    Abstracts

    Techniques for Handling Noise and Variability in Analog Circuits
    January 25-29, 2021

    EPFL Premises, Lausanne, Switzerland

    Random Mismatch Origins
    Marcel Pelgrom, Pelgrom Consult

    Circuit design greatly depends on the ability to control and reproduce process and device parameters. Statistical variations between otherwise identical components are generally described by “mismatch” parameters.  This lecture will analyze the origins of mismatch, such as random dopant fluctuations. Understanding and mitigating these effects requires statistical means.
    The general mismatch model will be discussed and compared to measurements. The application to the current variation in MOS transistors is analyzed. The relation to technological parameters, Finfet, SOI and design choices is explained.

    Analyzing Mismatch and Yield in Analog Circuits
    Marcel Pelgrom, Pelgrom Consult

    Analog ICs with differential operation are heavily affected by mismatch. In today’s advanced technologies every circuit from SRAM cell to an I-Q mixer must deal with statistical variations.  This lecture deals with handling the statistical effects in circuits, analyzing input referred random offsets and estimating yield. Examples start with the analysis of a simple differential pair, and are extended to opamps, voltage and current steering DACs, bandgaps and other analog circuits. The theory is also applied to timing chains, ring oscillators and yield analysis of flash converters.  Options to reduce the effect of mismatch and gradients are discussed.

    Layout Strategies to Reduce Offset
    Marcel Pelgrom, Pelgrom Consult

    After an introduction on elementary IC device characteristics and circuit analysis aspects (statistics, spread, fluctuations, parametric gradients), this lecture focuses on the main attention areas of mixed-signal circuit layout, namely electrical design related issues and technology related hazards. The design part discusses topics like IR drop, power supply loops, mirroring of lay-outs,  temperature gradients and design discipline. The technology part focuses on proximity and reticle effects, advanced lithography such as double patterning, layout induced mechanical stress asymmetries, and common centroid layout solutions.  The lecture finishes with a comprehensive set of guidelines.

    Offset, CMRR and PSRR
    Willy Sansen, KU Leuven

    Mismatch between transistors, resistors and capacitors causes severe limitations in the performance of differential circuitry. They are expressed by parameters such as offset, CMRR and PSRR. These sources of random and systematic mismatch are discussed in detail. The parameters are analyzed for differential pairs, current mirrors, operational transconductance amplifiers, etc. A number of design guidelines are put together for better matching.

    Variability in Bandgaps
    Willy Sansen, KU Leuven

    Precision applications require a bandgap reference, with an accurate temperature coefficient over a wide range of temperatures. It usually consists of a bipolar transistor in which a resistor develops a PTAT (proportional-to-absolute-temperature) voltage. It can also be realized with a MOST in weak inversion with appropriate temperature compensation. Mismatch between the transistor parameters leads to a high level of variability, which can only be reduced by trimming. Examples are given for both bipolar and CMOS technologies.

    Fundamentals of Noise in Electronic Devices
    Christian Enz, EPFL

    After variability, noise represents the ultimate limitations of analog circuits. Designers therefore need to be able to optimize circuits for low-noise operation. This lecture starts with the presentation of the mathematical tools needed for analyzing and optimizing noise in circuits. The definition of power spectral density and its use for the calculation of noise bandwidth and noise power are given. The different types of noise, their origin and properties are described, including thermal, shot and flicker noise. The noise models of different devices are then described with a special attention to the MOS transistor. The noise at RF is also described including the concept of noise matching with the noise factor and the other noise parameters. The lecture is illustrated with many examples.

    Noise Cancellation Techniques
    Willy Sansen, KU Leuven

    Wireless receivers all start with an LNA (Low-noise amplifier) to provide gain with very low noise and distortion. Impedance and noise matching is normally used at the input. The recent ones all provide wide-band performance, and use both noise and distortion cancellation. They yield higher FOM’s than hitherto possible. The Focus is on noise cancellation techniques, some of which are applicable to any amplifier or filter.

    Noise Sampling in Switched Capacitor Filters
    Willy Sansen, KU Leuven

    Switched-capacitor filters are preferred at low frequencies because they only require switches, capacitors and operational amplifiers. The matching between the capacitors determines the accuracy of the filter frequencies. Techniques are discussed to reduce the power consumption without increasing the noise levels. Numerical examples are given of several SC filter designs followed by examples of Sigma-Delta modulators using SC filters for noise shaping.

    Noise Analysis in Continuous-Time and Sampled-Data Circuits
    Christian Enz, EPFL

    Noise problems have always two aspects: the description and modeling of the physical noise sources in devices and the way this noise is propagating in the circuit to the output. Whereas the above lecture is dedicated to the noise sources, this part is focused on the understanding and modeling of the noise in circuits. It starts with the calculation of noise in continuous-time circuits. The analysis allows to identify which are the fundamental device and circuit noise parameters and how they can be optimized for low-noise. The effect of noise sampling and aliasing occurring in sampled-data circuits such as switched-capacitor (SC) circuits is then described. A simple technique for calculating noise power in SC circuits is then presented. Finally, the basic principles for reducing low frequency noise are presented: autozero and correlated-double sampling in sampled-data circuits and chopper stabilization in continuous-time circuits.

    Dynamic Offset-Cancellation Techniques
    Kofi Makinwa, TU Delft

    In amplifiers, component mismatch can easily cause offsets of several (tens of) millivolts. This can be reduced to the microvolt level by the application of dynamic techniques such as auto-zeroing and chopping. Compared to the alternatives, i.e. the use of large devices or trimming, the use of dynamic techniques has the added advantage of also reducing 1/f noise and drift, making it possible to design amplifiers that are thermal-noise limited. In this lecture, an introduction to auto-zeroing and chopping will be given, their pros and cons highlighted and recent advances in the state-of-the-art reviewed.

    Dynamic Element Matching Techniques
    Kofi Makinwa, TU Delft

    Component mismatch also limits the gain accuracy of amplifiers and the linearity of data converters. In such systems, the use of dynamic element matching (DEM) allows a trade-off to be made between speed and precision. The use of DEM allows gain accuracies of a few ppm to be realized even in standard CMOS processes, as well as data-converters whose SNDR can exceed 100dB. In this lecture, an introduction to DEM will be presented, and its application to precision amplifiers and highly linear data converters will be discussed.

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