SERDES Design for Wireline and Optical Communications

    March 25-28, 2019

    Registration deadline: February 25, 2019
    Payment deadline: March 11, 2019

    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, March 25

    8:30-10:00 am Introduction to NRZ and PAM4 Transceivers Behzad Razavi
    10:30-12:00 am PLL Design for Transmitters and Receivers Behzad Razavi
    1:30-3:00 pm High-Performance VCO Design Behzad Razavi
    3:30-5:00 pm Multiplexer Design, Examples of the State-of-the-Art Behzad Razavi

    TUESDAY, March 26

    8:30-10:00 am Transistor-Level Design of Linear Continuous-Time Equalizers Behzad Razavi
    10:30-12:00 am Transistor-Level Design of Decision-Feedback Equalizers Behzad Razavi
    1:30-3:00 pm Demultiplexers Behzad Razavi
    3:30-5:00 pm Examples of State-of-the-Art Behzad Razavi

    WEDNESDAY, March 27

    8:30-10:00 am Analog Clock and Date Recovery Circuits Behzad Razavi
    10:30-12:00 am Digital Clock and Data Recovery Circuits Behzad Razavi
    1:30-5:00 pm State-of-the-Art NRZ and PAM4 Transceiver Studies Behzad Razavi

    THURSDAY, March 28

    8:30-10:00 am Advance Signaling Methods and Circuits for Communication over Copper Armin Tajalli
    10:30-12:00 am Short Reach Transceiver Design Tradeoffs Armin Tajalli
    1:30-3:00 pm Slicer Design Armin Tajalli

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    SERDES Design for Wireline and Optical Communications
    March 25-28, 2019
    UC Santa Cruz, California, USA

    Abstract for the Course
    Behzad Razavi, UCLA

    This course is introduced to methodically teach the analysis and design of NRZ and PAM4 SERDES systems and their building blocks. For each function in the transceiver, the course begins with fundamental concepts and ramps up to state-of-the-art techniques and case studies.
    For transmitter design, we study clock-generation PLLs, multiplexers, and drivers, and for receivers, we deal with continuous-time linear equalizers, decision-feedback equalizers, clock and data recovery circuits, and demultiplexers. Emphasizing both high speeds and low power, we identify the design challenges and propose architecture and circuit techniques that improve the performance. We finally draw upon state-of-the-art NRZ and PAM4 transceivers to see what is possible today and reinforce the most robust design concepts.

    Advance Signaling Methods and Circuits for Communication over Copper
    Armin Tajalli, University of Utah, USA

    Moving toward data rates beyond 56 Gb/s, channel equalization becomes very challenging. To keep the energy consumption of serial data transceivers within the expected budget, industry is looking for more advanced signaling methods that use more efficiently the available frequency spectrum. This lecture introduces some advanced signaling methods such as Multi-Tone signaling, Repetition codes, and Cordal codes, that can be used to implement very low-power and high-speed links.

    Short Reach Transceiver Design Tradeoffs
    Armin Tajalli, University of Utah, USA

    Multi-chip module (MCM) technology has become very attractive for implementing high performance SoC systems. To reduce time to market, improve yield, and reduce product cost, today industry is moving more and more toward using MCM technology. In this type of systems, in which several dies are placed on the same substrate, high-speed and low-power serial communication between dies is critically important. Due to stringent energy budget, these systems employ many advance clocking and equalization techniques to keep the consumption low. This lecture presents the main tradeoffs in design of short reach serial data transceivers, which are widely used in modern SoC and MCM systems.

    Slicer Design
    Armin Tajalli, University of Utah, USA

    Slicers are considered to be the heart of each serial data receiver. A slicer is used to decide what is the data carried out by over the link. Precision, noise, and speed of operation of slicers are critically important. Reviewing some common circuit topologies, this lecture introduces few advanced techniques to implement very high-speed and low-noise slicer circuits.


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