PLLs and Oscillators

    June 25-29 2018
    Deadline for registration: May 22, 2018

    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, June 25

    8:30-10:00 am Fundamentals of Analog PLLs Michiel Steyaert
    10:30-12:00 am Interference Effects in PLLs Michiel Steyaert
    1:30-5:00 pm Spiral Inductor Interference, Deadzone and Phase Noise Michiel Steyaert

    TUESDAY, June 26

    8:30-12:00 am VCO Design Ali Hajimiri
    1:30-5:00 pm Jitter and Phase Noise in PLLs Ali Hajimiri

    WEDNESDAY, June 27

    8:30-12:00 am All-Digital PLL Architecture and Implementation Bogdan Staszewski
    1:30-3:00 pm Digitally-Controlled Oscillator (DCO) Bogdan Staszewski
    3:30-5:00 pm Time-to-Digital Converter (TDC) Bogdan Staszewski

    THURSDAY, June 28

    8:30-10:00 am Oscillator Basics: Feedback and Power Consumption Willy Sansen
    10:30-12:00 am RC-Oscillators Willy Sansen
    1:30-3:00 pm Designing XTAL and MEMS Oscillator from MHz to GHz David Ruffieux
    3:30-5:00 pm Low Phase Noise and Low Jitter 0.1-10GHz VCO David Ruffieux

    FRIDAY June 29

    8:30-12:00 am Fractional-N PLLs for Frequency Synthesis Ian Galton
    1:30-3:00 pm FDC-Based Digital PLLs Ian Galton

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    PLLs and Oscillators
    June 25-29, 2018

    EPFL Premises, Lausanne, Switzerland

    Fundamentals of Analog PLLs
    Michiel Steyaert, KU Leuven

    Abstract to come.

    Interference Effects in PLLs
    Michiel Steyaert, KU Leuven

    Different interference effects in PLLs are discussed. First de Dead-zone in phase detectors. Secondly, the design of prescalers and the effect of mismatch in noise performance in fractional-N. Finally the RF and Power supply coupling effects.

    Spiral Inductor Interference, Deafzone and Phase Noise
    Michiel Steyaert, KU Leuven

    Abstract to come.

    VCO Design – Jitter and Phase Noise in PLLs
    Ali Hajimiri, Caltech

    We start this lecture with an overview of the VCO noise concepts and some of the classical work in this area. We elucidate some of the basic properties of oscillator phase noise through several thought experiments. Then we go through a step-by-step development of a time-varying noise model for oscillators and discuss the evolution of noise in an oscillator from its physical sources to frequency and amplitude fluctuations. In this process, we see how low frequency noise sources affect the oscillator behavior and discuss the impact of time-varying and correlated noise source. In the second part of the lecture, we discuss how the new design insights obtained from our model leads to novel VCO topologies that overcome some of their basic challenges and limitations. We discuss additional trade-offs in VCOs and apply them in the context of several practical design examples for a broad range of frequencies and applications. Finally, we focus our attention to the noise process in phase-locked loops and analyze it using a parallel time- and frequency-domain analysis of noise in PLLs.

    All-Digital PLL Architecture and Implementation
    Bogdan Staszewski, TU Delft

    The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits are readily estimated and compensated using “free” but powerful digital logic. This lecture presents a system level view of the ADPLL:

    1. Principles of phase-domain frequency synthesis 2. ADPLL closed-loop behavior 3. Direct frequency modulation of ADPLL 4. Alternative TX architectures using ADPLL and PA regulator 5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design

    Digitally-Controlled Oscillator (DCO)
    Bogdan Staszewski, TU Delft

    A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but with a significant difference in one of the components: instead of continuously tuned varactor (variable capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed in either high or low capacitive state. The composite varactor performs digital-to-capacitance conversion. This lecture presents a circuit system level view of DCO.

    Time-to-Digital Converter (TDC)
    Bogdan Staszewski, TU Delft

    A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay (about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level implementation issues.

    Oscillator Basics: Feedback and Power Consumption
    Willy Sansen, KU Leuven

    Oscillators are feedback amplifiers, with specific requirements on gain and phase shift. These Barkhausen conditions are illustrated for the generic single-transistor oscillator and a large number of differential oscillators. Both crystals and spiral inductors can be used to determine the oscillation frequency and power consumption. Automatic-gain-control is normally required to stabilize the operating point and the output swing, which both affect the phase noise and the harmonic content.

    Willy Sansen, KU Leuven

    Oscillators without inductors are less precise but can operate at very low power levels. Relaxation oscillators are discussed first. They can be used for real-time clock applications. They are meant to replace crystal oscillators as they can be switched on and off more rapidly. Moreover they can be fully integrated. Minimum power consumption is required for applications such as wireless sensor nodes. Finally ring oscillators and sinusoidal oscillators are discussed as well.

    Designing XTAL and MEMS Oscillator from MHz to GHz
    David Ruffieux, CSEM

    This course will first review the fundamental theory of Pierce type or three-points oscillators so as to determine the oscillation conditions and minimum figure of merit requirement for different type of electro-mechanical (quartz, MEMS, FBAR) resonators. Amplitude regulation loop will be discussed so as to guarantee fast start-up, robust operation and well-controlled phase noise performance. Alternative differential oscillator structures will then be presented and the analysis extended to VCXO, DCXO, DTCXO implementations including their limitations. Topologies for rail to rail amplifiers/dividers and their impact on jitter will be studied. At last, phase noise, accumulated timing jitter and Allan deviation metrics and their inter-relations will be reviewed as well as ways to simulate and measure them.

    Low-Phase Noise and Low-Jitter 0.1-10 GHz VCO
    David Ruffieux, CSEM

    Several LC VCO structures will first be analyzed and their main trades-off discussed. Then the lecture will concentrate on the optimization of LC tank elements to reach a given tuning range, reduce their supply noise sensitivity, maximize their Q-factor and study how to trade VCO power and phase noise performances . Digitally controlled varactors for coarse tuning and DCO implementations will also be covered including techniques such as dynamic element matching to improve DNL and fine frequency interpolation via delta sigma modulation switching of tiny capacitors. Topologies for quadrature LO generation will be investigated followed by a short discussion on LO buffers. Eventually, comparison with non-LC based VCO will be made.

    Fractional-N PLLs for Frequency Synthesis
    Ian Galton, UC San Diego

    This lecture explains the extension of integer-N PLLs to fractional-N PLLs for both fine tuning resolution and in-loop VCO modulation. It presents an overview of modulus quantization noise shaping techniques, tradeoffs associated with quantization noise shaping order and PLL loop bandwidth, non-ideal effects of particular concern in fractional-N PLLs such as charge pump nonlinearities and data-dependent multi-modulus divider delays, techniques for increasing loop bandwidth, simulation techniques, and case studies of example circuits and applications.

    FDC-Based Digital PLLs
    Ian Galton, UC San Diego

    While both analog and digital fractional-N PLLs introduce quantization error, the majority of digital PLLs developed to date introduce quantization error with higher power or higher spurious tones than comparable analog PLLs. Digital PLLs based on second-order delta-sigma frequency-to-digital conversion address this problem in that their quantization noise ideally is equivalent to that of analog PLLs with second-order delta-sigma modulation. This talk describes the underlying theory and practical implementation of digital PLLs based on frequency-to-digital conversion and illustrates the presented concepts with IC implementation details and measured results.


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Time Zone

  • Lausanne
  • TU DELFT The Netherland
  • UC Santa Cruz

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