High-Performance Data Converters

    March 25-29, 2019

    Registration deadline: February 25, 2019
    Payment deadline: March 11, 2019

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, March 25

    8:30-10:00 am Overview of High-Speed Data Converters Marcel Pelgrom
    10:30-12:00 am Fundamental Limitations Marcel Pelgrom
    3:30-5:00 pm Flash ADCs Marcel Pelgrom

    TUESDAY, March 26

    8:30-10:00 am Interleaved ADCs Marcel Pelgrom
    10:30-12:00 am
    & 1:30-3:00
    Mismatch-Shaping Multi-bit DACs Ian Galton
    3:30-5:00 pm SAR ADCs Klaas Bult

    WEDNESDAY, March 27

    8:30-10:00 am Comparison of ADC Architectures Klaas Bult
    10:30-12:00 am ADC Building Blocks Klaas Bult
    1:30-3:00 pm Introduction to Pipeline ADCs Ian Galton
    3:30-5:00 pm Pipeline ADCs with Digital Calibration Ian Galton

    THURSDAY, March 28

    8:30-12:00 am Power Dissipation in ADCs Klaas Bult
    1:30-3:00 pm VCO-based ADC Techniques Ian Galton
    3:30-5:00 pm DEM for Nyquist-Rate Current-Steering DACs Ian Galton

    FRIDAY, March 29

    8:30-12:00 am High-Speed DACs Klaas Bult
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    Abstracts

    High-Performance Data Converters
    March 25-29, 2019
    UC Santa Cruz, California, USA

    Overview of High-Speed Data Converters
    Marcel Pelgrom, Pelgrom Consult

    High-speed data converters are the basic ingredient in many data conversion techniques. Technology and design choices influence the way a converter can achieve its performance goals. In this overview the basic sampling and quantization mechanisms will be reviewed followed by some techniques to circumvent or reduce unwanted effects.

    Fundamental Limitations
    Marcel Pelgrom, Pelgrom Consult

    Matching of components, noise, distortion and jitter are the dominant factors that limit high-speed converter performance. Technology and design choices influence the way these limitations appear in the final conversion result. The basic mechanisms will be discussed and techniques to circumvent or reduce unwanted effects will be presented.

    Flash ADCs
    Marcel Pelgrom, Pelgrom Consult

    The flash ADC is the basic building block of many ADC topologies. Various aspects of the design of a flash ADC will be considered: ladder impedance, comparator design, decoding and interpolation. The design choices will be illustrated with examples in which also trade-offs on a design level will be considered.

    Interleaved ADCs
    Marcel Pelgrom, Pelgrom Consult, The Netherlands

    The introduction of massive parallel analog-to-digital conversion or interleaved converters, has allowed to process wide bandwidths at moderate resolutions. This talk will survey the theoretical background, the various design choices and the errors caused by unequal parallel paths.

    Mismatch-Shaping Multi-bit DACs
    Ian Galton, UC San Diego, USA

    Multi-bit quantization has all but supplanted single-bit quantization in new designs of high-performance delta-sigma ADCs and DACs, resulting in significant data conversion performance improvements over the last decade. Mismatch-shaping dynamic element matching has enabled this transition by eliminating component mismatches as the limiting source of error in multi-bit designs. This tutorial talk will review delta-sigma ADCs, describe the component matching problem that arises in delta-sigma ADCs with multi-bit quantization, and explain the mismatch-shaping dynamic element matching solution in detail. Topics include qualitative and quantitative explanations of how error from component mismatches is spectrally shaped without knowledge of the mismatches, different mismatch-shaping DAC topologies and their limitations, and implications of mismatch-shaping DACs for system and circuit design of delta-sigma ADCs.

    SAR ADCs
    Klaas Bult, Bult Consult, The Netherlands

    Dating back to the 1970s, SAR ADCs have once again become popular but for a different reason. It has been recognized that these ADCs better lend themselves to scaled technologies as they employ few analog functions. This presentation deals with the basic properties of SAR ADCs and their pros and cons. It is shown that these architectures can be realized with zero static power consumption but they need complex DACs and suffer from a low speed.

    Comparison of ADC Architectures
    Klaas Bult, Bult Consult, The Netherlands

    In this lecture we will discuss the various architectures (Flash, Folding, SAR, Pipeline, Pipelined-SAR, etc.) and how the building blocks appear in these architectures and which demands these architectures put on these blocks.

    ADC Building Blocks
    Klaas Bult, Bult Consult, The Netherlands

    Most ADCs are built from blocks like DACs, Comparators, Amplifiers and logic. We will go into detail on all of these blocks, with different implementations but also very specifically what they have in common. We will also make a fundamental estimate of their power dissipation based on the specifications like for instance Dynamic Range and Sampling Frequency.

    Introduction to Pipeline ADCs
    Ian Galton, UC San Diego

    This lecture presents a detailed introduction to pipelined ADCs. First, the system-level concepts underlying pipelined ADCs are presented in terms of a particular pipelined ADC example, including sensitivity to non-ideal behavior of the various pipeline components. Architectural tradeoffs associated with changing the number of bits per stage and number of stages are then presented. Finally, the specific pipelined ADC example is revisited and circuit-level issues and tradeoffs are introduced.

    Pipeline ADCs with Digital Calibration
    Ian Galton, UC San Diego, USA

    This lecture presents digital background calibration techniques that suppress error introduced by non-ideal analog circuitry. Pipelined ADCs are highly sensitive to mismatches among certain components and residue amplifier gain error and nonlinearity, especially when designed for low supply voltages. The digital calibration techniques address these problems. The system-level concepts and circuit-level implementation issues are presented in the context of a 1.2 V CMOS pipelined ADC design example wherein the techniques are shown to enable state-of-the-art performance.

    Power Dissipation in ADCs
    Klaas Bult, Bult Consult, The Netherlands

    In tese 2 blocks we will discuss the above mentioned architectures and use the Power Dissipation Estimates derived in “ADC Building Blocks” and with that make an estimate of the Power Dissipation of a certain architecture based on it’s specifications. These estimates will be compared to all published ADCs in ISSCC and VLSI of the past 20 years (using the overview that Boris Murmann updates every year on his website). This comparison with real data shows that this method of estimating power yields
    very realistic results with numbers close to published data. This method moreover allows us to make estimates of not yet existing ADCs based on their specifications. It allows to make choice between architecture based on it’s performance and expected power dissipation. This will make for a much better starting point than what is usually the case in real designs.

    VCO-based ADC Techniques
    Ian Galton, UC San Diego, USA

    ADCs based on ring oscillator voltage controlled oscillators (VCOs) enabled by digital calibration have the functionality of conventional continuous-time delta-sigma ADCs, but without the need for analog integrators, feedback DACs, comparators, reference voltages, or low-jitter clocks. Therefore, they use much less area than comparable conventional delta-sigma ADCs, are well-suited to advanced CMOS technology, and can easily support reconfigurability. This lecture will describe the principles of VCO-based ADCs, their limitations, techniques such as digital calibration for addressing their limitations, and will present case studies of example IC implementations.

    DEM for Nyquist-Rate Current-Steering DACs
    Ian Galton, UC San Diego, USA

    In high-resolution (>11 ENOB) Nyquist-rate DACs, mismatches among nominally identical components incurred during IC fabrication as well as possible systematic circuit and layout mismatches cause harmonic distortion and often limit overall DAC linearity. This talk describes recently-developed segmented DEM techniques applicable to high-resolution Nyquist-rate DACs that eliminate pulse shape, timing, and amplitude errors arising from component mismatches as sources of nonlinear distortion.

    High-Speed DACs
    Klaas Bult, Bult Consult, The Netherlands

    Introduction to current-steering DACs. Common error mechanisms; error sources affecting amplitude and timing. Code dependent output-impedance; solutions, measurements, comparison to theory and literature.

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