Energy-Constrained Integrated Systems

     

    December 10-14, 2018

    Early registration deadline: November 23, 2018
    Payment deadline: November 26, 2018

    registration
    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, December 10

    8:30-10:00 am System-Level (Over)View, Fundamental Tradeoffs, Verticals Massimo Alioto
    10:30-12:00 am Co-Design Methodologies and Design Space Exploration Eduard Alarcon
    1:30-3:00 pm System-Wide Adaptive On-Chip Power Management Eduard Alarcon
    3:30-5:00 pm Low-Energy Wireless Communications and
    Transceivers, Part I
    Teerachot Siriburanon

    TUESDAY, December 11

    8:30-12:00 am Low-Energy Wireless Communications and
    Transceivers, Part II
    Teerachot Siriburanon
    1:30-5:00 pm Low-Power, Information-Preserving Analog Interfaces Boris Murmann

    WEDNESDAY, December 12

    8:30-12:00 am Low-Power, Information-Preserving Analog Interfaces
    (cont’d)
    Boris Murmann
    1:30-5:00 pm Ultra-Low Power and Adaptive Digital Techniques, Part I Massimo Alioto

    THURSDAY, December 13

    8:30-10:00 am Ultra-Low Power and Adaptive Digital Techniques, Part II Massimo Alioto
    10:30-12:00 am
    & 1:30-5:00 pm
    Wearable Sensor, Network, and Packaging for Mobile Healthcare Systems Hoi-Jun Yoo

    FRIDAY, December 14

    8:30-10:00 am Human Intelligence System with Bio-Inspired SoC Hoi-Jun Yoo
    10:30-12:00 am
    & 1:30-3:00 pm
    Distributed Sensors Platforms and Energy-Centric
    System Optimization (Parts I and II)
    Jan Rabaey
    3:30-5:00 pm Case Studies of Energy-Constrained Systems: IoT, Swarms Jan Rabaey
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    Abstracts

    Energy-Constrained Integrated Systems
    December 10-14, 2018
    Singapore

    System-Level (Over)View, Fundamental Tradeoffs, Verticals
    Massimo Alioto, University of Singapore, Singapore

    This introductory module presents the “big picture” of the challenges and the opportunities related to the design of tightly energy-constrained silicon systems. System constraints and design metrics are linked to practical applications, such as sensor nodes for the Internet of Things, wearables, biomedical and implantable devices. Fundamental tradeoffs (e.g., communication-computation-memory) are explored for time- and event-driven paradigms, while considering a wide range of architectures from heavily duty cycled to always-on. Surveys on the state of the art are extensively used to gain an understanding of technological trends and system requirements. Case studies illustrate the benefits of across-level thinking, system-level optimization, run-time co-adaptation and energy-quality scaling, among the other “big ideas” that drive the design of energy-constrained integrated systems.

    Co-Design Methodologies and Design Space Exploration
    Eduard Alarcon, University of Catalunia, Spain

    The notion of optimized design and design-oriented parametric space exploration will be presented as a central methodology in advanced silicon designs with stringent requirements. This design approach will be illustrated with various examples, including on-chip power supplies, high frequency circuits with nanoscale devices and on-chip antennas. Co-design methodologies will be presented between various vertical design layers, from device up to circuit and system levels. Design examples will emphasize the benefit of a tight joint characterization, modelling and circuit co-design approach, both within subsystems and across subsystems, a crucial aspect in the era of complex energy-constrained integrated systems on a chip. A design-oriented scalability analysis will show the effects of downscaling technology on circuit design performance. System-level performance scalability with metrics capturing system attributes will be discussed.

    System-Wide Adaptive On-Chip Power Management
    Eduard Alarcon, University of Catalunia, Spain

    This lecture will provide a system perspective for on-chip power management by surveying the device, circuit and architectural options to implement high-efficiency high-density low-power on-chip supplies together with their controller implementations, for both many-core computer architectures, battery-operated terminals and energy-harvesting-powered wireless sensor nodes and implants. Use cases of fast adaptive power supply would encompass Adaptive Voltage Scaling for processors, and adaptive power supplies in envelope tracking polar RF transmitters. The design examples will highlight vertical methodologies for assessing the system level impact of circuit-level non-idealities and impairments.

    Low-Energy Wireless Communications and Transceivers
    Teerachot Siriburanon, Dublin Technical University, Ireland

    Internet-of-Things (IoT) imposes severe requirements on ultra-low power (ULP) consumption of radio frequency transceivers. We address this challenge by exploiting digitally intensive approaches to frequency synthesizer, transmitter and receiver in advanced CMOS technology.
    The first part presents advances in discrete-time receiver designs that offer new alternatives with simpler and technology-scalable switched-capacitor circuits and easy calibration of intermediate frequency and band-pass selection based on capacitor ratios, which are less sensitive to process variations. New passive charge-domain switched-capacitor filter topologies and accurate control of sampling rates, both of which benefit from technology scaling and enable easier-to-design low-power solutions, are introduced.
    The second part covers the digital manner of architecting a PLL and transmitter optimized at low-voltage operation. All-digital PLL offers transfer-function precision for two-point frequency modulation, ease of calibration and instantaneous shut-down capability, while allowing to operate at or below the threshold voltage of transistors. The oscillator and power amplifier exploit resonant networks for low-voltage operation with high efficiency.

    Low-Power, Information-Preserving Analog
    Boris Murmann, Stanford University, USA

    This four-lecture module begins with an exploration of fundamental efficiency limits in amplification, filtering and data conversion. Motivated by the findings, we then introduce the concept of analog-to-information interfaces, which can break conventional limits by leveraging a-priori information about the signal source. The various methods of constructing A-to-I interfaces will be discussed and the concepts of compressed sensing will be highlighted in a deep-dive. The remainder of the module is dedicated to case studies including a compressed sensing RF receiver, an innovation-rate sampling ultrasound imager, a sub-Nyquist training approach for digital PA pre-distorters, a log-domain feature extractor for object detection, and compressive interfaces for brain-machine interfaces.

    Ultra-Low Power and Adaptive Digital Techniques
    Massimo Alioto, University of Singapore, Singapore

    This module introduces a comprehensive perspective on the available design techniques for energy-efficient digital sub-systems, from fundamental concepts to advanced topics. Nearly-minimum energy computation and wide energy-peak performance scaling are analyzed from a design perspective, introducing fresh approaches to achieve wide adaptation. Novel conceptual tools are provided to rapidly estimate the impact of design and process parameters on the achievable energy-performance design target, and the necessary design margin. Practical methods to quickly estimate the impact of leakage and process/voltage/temperature variations are introduced and applied to case studies, empowering the designer with a deeper insight into the related tradeoffs.

    Wearable Sensor, Network, and Packaging for Mobile Healthcare Systems
    Hoi-Jun Yoo, KAIST, Republic of Korea

    Compact and convenient healthcare systems made of CMOS ICs start low-cost, ubiquitous healthcare services. Mobile healthcare systems, such as portable, wearable and implantable systems, and their circuits and systems are introduced. The compact CMOS circuits for the sensor read-out, ADC, and wireless communication will be explained. Also, Fabric, which is used as system integration substrate, and a new integration scheme by which the CMOS ICs will be directly bonded on the fabric, will be introduced. The circuits and systems developed by KAIST will be presented including Bandage type body signal monitors, Sleep monitoring system, Smart Acupuncture systems, Electrical impedance tomography, and Mental healthcare management systems.

    Human Intelligence System with Bio-Inspired SoC
    Hoi-Jun Yoo, KAIST, Republic of Korea

    For Intelligence mobile/Embedded devices such as smart glasses, autonomous vehicles, and intelligent robots, AI technologies (such as CNN, RNN, Pattern recognition and so on) are implemented with low-power and high-performance SoC. KAIST’s approach is integrating both sides of brain, right-brain for “approximation and adaptation hardware” and left-brain for “precise and programmable Von Neumann architecture”. By mimicking right-brain, specialized intelligent hardware is proposed with analog-digital mixed-mode circuit, adaptive low-bit precision and so on. And, by mimicking left-brain, multi-core processor for precise computations including software AI are integrated on the same silicon chip.

    Distributed Sensors platforms and Energy-Centric System Optimization, Part I
    Jan Rabaey, UC Berkeley

    One of the main challenges in the design and optimization of sensor networks and IoT deployments is the distributed nature of the system. The main goal is to design a system that meets constraints in terms of functionality, operational life-time, robustness, responsiveness and cost. The designer has a number of parameters to play with including the trade-off between communication and computation, the communication protocols and the network design, distributed power management and duty cycling, and intelligent management. In this lecture, we will discuss the various options and the possible trade-offs.

    Distributed Sensors platforms and Energy-Centric System Optimization, Part II
    Jan Rabaey, UC Berkeley

    Another concern in the design of distributed sensor and IoT platforms is the dynamic nature of the system, as well as the need to share the platform over different applications with different constraints and requirements. Making IoT truly portable and easily deployable requires the availability of an abstraction layer that disaggregates the applications from the specifics of the physical realization and the available resources, in other words “an operating system (OS)”. While this approach has worked very effectively for microprocessors and smartphones, the IoT OS challenge is that the system is distributed and dynamic. In this presentation, we will introduce the concepts and components of the SwarmOS and the Global Data Plane (GDP), and compare this to the industry state-of-the-art.

    Case Studies of Energy-Constrained Systems: IoT, Swarms
    Jan Rabaey, UC Berkeley

    At the end of this weeklong course, it makes sense to bring all the components together by studying the state-of-the-art in IoT and Sensor Network deployments in academia, industry, government and consumer. We will also spend some time looking forward on what we may expect in the foreseeable future. Finally, some time will be reserved for discussion and Q&A regarding all aspects of sensor network design, deployment and management.


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