Advanced Analog Circuit Design

    March 26-30, 2018
    Deadline for registration: February 19, 2018

    Course material will be distributed only if fees have been paid by the deadline for payment.

    MONDAY, March 26

    8:30-10:00 am Opamp Stability and Optimization David Johns
    10:30-12:00 am
    & 1:30-3:00 pm
    Low Power OpAmp Design and Biasing David Johns
    3:30-5:00 pm Circuit Noise Limitations David Johns

    TUESDAY, March 27

    8:30-12:00 am Time Assisted Analog Design Pavan Hanumolu
    1:30-5:00 pm Circuit Techniques for OpAmp Speed and
    Accuracy Improvements
    Vadim Ivanov

    WEDNESDAY, March 28

    8:30-10:00 am Voltage References Vadim Ivanov
    10:30-12:00 am
    & 1:30-3:00 pm
    Continuous-Time Filters Boris Murmann
    3:30-5:00 pm CMOS Switched-Capacitor Circuit Design Boris Murmann

    THURSDAY, March 29

    8:30-10:00 am Offset and 1/f Noise Reduction Techniques Boris Murmann
    10:30-12:00 am
    & 1:30-3:00 pm
    Gm/ID-based Design of Amplifier Circuits Boris Murmann
    3:30-5:00 pm Digitally Enhanced Analog Design Ian Galton

    FRIDAY, March 30

    8:30-12:00 am Digitally Enhanced Analog Design Ian Galton

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    Advanced Analog Circuit Design
    March 26-30, 2018
    UC Santa Cruz, California, USA

    Opamp Stability and Optimization
    David Johns, University of Toronto

    This talk will discuss stability as it relates to small and larger circuits. Topics covered include loop-gain/poles relationship, return-ratio, blackman-impedance, pole-splitting, dealing with positive zero, and nested-miller compensation.

    Low Power OpAamp Design and Biasing
    David Johns, University of Toronto

    This talk will discuss opamp design with an emphasis on low power and biasing approaches. Topics covered include weak/strong-inversion biasing, constant-current/PTAT/constant-Gm biasing, differential, two/single-stage/multistage opamps, common-mode feedback and negative resistors.

    Circuit Noise Limitations
    David Johns, University of Toronto

    Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.

    Time Assisted Analog Design
    Pavan K. Hanumolu, University of Illinois

    Time-based signal processing is emerging as a viable alternative to analog signal processing traditionally performed in voltage, current, or charge domains. This tutorial discusses time-based techniques to implement classical analog functions such as filtering, control and data conversion. Time-based circuits using voltage controlled ring oscillators will be presented and their design tradeoffs will be elucidated with the aid of circuit design examples.

    Circuit Techniques for OpAmp Speed and Accuracy Improvement
    Vadim Ivanov, Texas Instruments

    Presented is a top down design process of the OpAmps based on the structural design methodology. We will start from selection of the gain structure, followed by the implementations of gain structures as well as gradual addition of various specific functions like PSRR/CMRR improvement, slew enhancement, overload recovery. We will consider offset improvement by trimming as well as by auto-zeroing and chopping, high-and low-voltage design specifics. Most of the circuits solutions were not published before and have been used in recent industrial ICs. Yet it is not another cookbook with analog circuit recipes. The goal of this presentation is to arm the engineers with a tool helping to invent the solution for any analog design problem and, at the same time, be reasonably sure that this solution is one of the best possible for any given process and set of constraints.

    Voltage References
    Vadime Ivanov, Texas Instruments

    Discussed are error sources of the bandgap voltage references and techniques for improving their accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with chopping offset elimination, output buffer with mOhm output impedance and fast settling on load changes; single- dual and triple temperature trimming; packaging requirements; testing and application particulars. Also presented circuit solutions for reverse bandgap reference, operational from 0.9V supply, and reference structure and implementations with nanoampere consumption.

    Continuous-Time Filters
    Boris Murmann, Stanford University

    Continuous-time filters play an important role in many communication systems and at the data conversion interface, where they are required for anti-aliasing and reconstruction. This module begins by reviewing the basic s-domain filter approximations and then looks into implementations strategies. We review active RC and gm-C topologies and study their imperfections and sensitivities to nonideal effects.

    CMOS Switched-Capacitor Circuit Design
    Boris Murmann, Stanford University

    Discrete-time signals, Laplace and z-transform; Basic building blocks (opamps, switches, capacitors); Sample-and-hold circuits; SC integrators, bilinear filters and and biquads; SC amplifiers; Correlated double sampling and chopper stabilization; Nonideal effects and their correction.

    Offset and 1/f Noise Reduction Techniques
    Boris Murmann, Stanford University

    The design of precision analog interfaces in CMOS is severely impaired by offset, offset drift and 1/f noise. The material covered in this module analyzes these impairments in detail and reviews the common solutions for their remedy: chopping, autozeroing, correlated double sampling and offset stabilization. We will discuss the residual nonidealities as well as pros and cons of each technique and review typical application examples. In addition, we will survey recent advances in the state-of-the-art.

    Gm/ID-based Design of Amplifier Circuits
    Boris Murmann, Stanford University

    The majority of textbook material on CMOS analog circuit design is based on the square-law model. While this model remains useful for teaching, it has become too inaccurate for design in nano-scale CMOS. This module presents a systematic design methodology that bridges this gap using Spice-generated look-up tables. We interpret these data based on the transistor’s inversion level, employing gm/ID as a proxy and key parameter for design. With the inclusion of other width-independent figures of merit (gm/Cgg, gm/gds, etc.), this allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. Since this entire flow is driven by Spice data, we maintain close agreement between the desired specs and the circuit’s simulated performance. The presented material will detail the inner workings of this approach and illustrate it using two amplifier design examples (folded cascode and two-stage OTA).

    Digitally Enhanced Analog Design
    Ian Galton, UC San Diego

    The design of analog circuit blocks such as data converters and PLLs is particularly challenging in highly-scaled CMOS technology wherein low supply voltages, high device nonlinearity, poor signal isolation, and device leakage limit the effectiveness of traditional analog circuit topologies. Increasingly, digital signal processing techniques and new digital-like analog circuits that exploit the strengths of highly-scaled CMOS technology are used to enable high-performance analog functionality. This lecture will describe several such digital enhancement techniques, including dynamic element matching, digital techniques to measure and cancel mismatch noise and harmonic distortion, and VCO-based ADCs.


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