- Practical Aspects in Mixed-Signal ICs

August 29 – September 2, 2016                                     Deadline for registration: July 13, 2016            registration

MONDAY, August 29

8:30 – 10:00 am Trade-off between Analog and Digital – The Impact of
Technology Scaling
Jan Rabaey
10:30 – 12:00 am Ultra Low-Power Mixed Signal Interfaces Jan Rabaey
1:30 – 5:00 pm Noise Coupling in Mixed-Mode ICs: Mechanisms,
Simulation, Measurement
Tim Schmerbeck

TUESDAY, August 30

8:30 – 10:00 am Noise Coupling in Mixed-Mode ICs: Design Strategy,
Hardware Example
Tim Schmerbeck
10:30 – 12:00 am Design for Electrostatic Discharge (ESD) Robustness in Silicon ICs Tim Schmerbeck
1:30 – 5:00 pm Digitally-Assisted Analog Circuits Marc Pastre

WEDNESDAY, August 31

8:30 – 10:00 am Offset and CMRR: Random and Systematic Willy Sansen
10:30 – 12:00 am Fully-Differential Amplifiers Willy Sansen
1:30 – 3:00 pm Bandgap Voltage References Willy Sansen
3:30 – 5:00 pm ESD (Continued) Tim Schmerbeck

THURSDAY, September 1

8:30 – 10:00 am Noise Calculation and Simulation in SC & CT Circuits Christian Enz
10:30 – 12:00 am Noise and Offset Reduction Techniques Christian Enz
1:30 – 5:00 pm Matching Impairments in Mixed-Mode ICs Herman Casier

FRIDAY, September 2

8:30 – 10:00 am Modeling and Simulation of Mixed-Mode Circuits Pavan Hanumolu
10:30 – 12:00 am Interference Effects: CMRR/PSRR Michiel Steyaert
1:30 – 3:00 pm Design for EMC Michiel Steyaert


August 29 – September 2, 2015
EPFL Premises, Lausanne, Switzerland

Trade-off between Analog and Digital – The Impact of Technology Scaling
Jan Rabaey, UC Berkeley

For over 5 decades, technology scaling has served to reduce the cost of electronic components and functionality. The same trend is still continuing today even do some of the traditional scaling strategies such as reducing supply voltages and thresholds are hitting bounds. However, there exists a perception that technology scaling primarily serves digital design, and that analog circuitry is better off with older technologies. In this lecture, we examine the trade-off between analog and digital in the nanometer era. A number of concrete examples will be used to illustrate the possible trade-offs.

Ultra Low-Power Mixed Signal Interfaces
Jan Rabaey, UC Berkeley

The growing importance of wireless sensor nets, ubiquitous electronics and biomedical interfaces (just to name a few) has spurred a need for mixed-signal interfaces that use only uWatts of power and hence can operate from scavenged energy. In the digital domain, sub-threshold operation at very low supply voltages is a common approach to enable ultra-low power (ULP) realization. These techniques do not translate well to the analog, mixed-signal and RF domains, where SNR and dynamic range considerations limit the scope of the supply voltage reduction. Yet, a careful balancing of the trade-off between analog and digital circuitry also allows for ULP mixed-signal to be a reality. In this lecture, the basic challenges and ideas in ULP mixed-signal are discussed, complemented with concrete case studies.

Noise Coupling in Mixed-Mode ICs: Mechanisms/Simulation/Measurement
Tim Schmerbeck, IBM

Survey of practical aspects of key analog and analog/digital interaction problems: Sources of noise. Methods of coupling. Effects of substrate referencing, power distribution, chip signal isolation/shielding techniques, packaging, card layout and circuit topology on noise. Analysis and modeling of particular analog and mixed signal noise problems along with experimental data results: Modeling and predicting chip/package noise prior to semi-conductor processing; Chip substrate modeling.

Noise Coupling in Mixed-Mode ICs: Design Strategy/Hardware Example
Tim Schmerbeck, IBM

Design strategies for reducing noise with emphasis on a product hardware example. Noise prevention techniques, noise reduction techniques, and noise rejection techniques. Actual hardware experiences along with techniques, methodologies, and strategies for analog mixed-signal noise reduction.

Design for Electrostatic Discharge (ESD) Robustness in Silicon Integrated Circuits
Tim Schmerbeck, IBM

A general treatment of the causes and prevention of chip ESD vulnerability including the ANSI ESD models with testing & simulation methods; a comprehensive treatment of common ESD protection structures; and how to design to accommodate needed protection levels. The emphasis will be on the practical application principals for designers.

Digitally-Assisted Analog Circuits
Marc Pastre, EPFL

To relieve the extreme design constraints in analog circuits, digital calibration becomes a must. It allows low-precision components to be used in high-performance systems. This course presents sub-binary radix DACs and their use for automatically calibrating analog circuits and systems. Their implementation is detailed and several case studies presented.

Offset and CMRR: Random and Systematic
Willy Sansen, KU Leuven

Random mismatch between the equally-designed transistors in a differential pair causes offset and reduction of both the CMRR and the PSRR. This phenomenon of random mismatch is discussed in detail. Its relevance is analyzed for differential pairs, current mirrors, etc. It is followed by a number of design guidelines for better matching.

Fully-Differential Amplifiers
Willy Sansen, KU Leuven

In mixed-mode design all circuits have to be fully differential. Therefore common-mode feedback amplifiers have to be included to ensure proper biasing and common-mode rejection. They are subject to specifications such as high frequency performance and low power consumption. All possible schematics are reviewed and compared.

Bandgap Voltage References
Willy Sansen, KU Leuven

Abstract to come.

Noise Calculation and Simulation in SC & CT Circuits
Christian Enz, EPFL

Basic devices noise models with particular emphasis on MOSFET. How good are the noise models available in MOSFET compact models? Noise calculation methods in continuous-time (CT) linear circuits. Different noise simulation methods: small-signal, transient noise, PNoise (SpectreRF). Practical CT and SC filter examples.

Noise and Offset Reduction Techniques
Christian Enz, EPFL

Autozero (AZ) and correlated-double sampling (CDS) techniques. Effect of AZ on white and 1/f noise. Residual offset. AZ implementations. Chopper Stabilization (CHS) technique. Equivalent dc gain. Effect of CHS on noise. Residual offset. CHS implementations. Noise and offset trade-off.

Matching Impairments in Mixed-Mode ICs
Herman Casier, Consultant

Random matching is a well known limitation for mixed-signal circuit design but this lower limit is often degraded or even dominated by systematic errors induced by processing imperfections, violation of physical device limits and environmentally induced gradients at chip level. Most of these effects are not or are difficult to include in the design flow. Several effects, such as mechanical stress, dielectric relaxation, degradation and thermal gradients are discussed in detail.

Modeling and Simulation of Mixed-Mode Circuits
Pavan K. Hanumolu, University of Illinois

Performing transistor-level simulations of mixed-mode circuits can be very time consuming. This makes performing design space exploration and circuit optimization very difficult and some times even infeasible. This tutorial discusses ways to model and simulate large mixed-mode circuits using commonly used commercial tools. Simulation examples of  mixed-mode circuits such as phase-locked loops will be discussed.

Interference Effects: CMRR/PSRR
Michiel Steyaert, KU Leuven

Some EMC interference effects in integrating RF circuits are addressed and discussed. The coupling mechanism of different building blocks to the sensitive RF circuits are addressed. Design techniques for high power supply rejection ratio in basic analog building blocks are studied.

Design for EMC
Michiel Steyaert, KU Leuven

Introduction to EMC problems: EMI, EME, EMS, charge pumping. EMS design techniques on basic building blocks: principles, current mirror, input and output structures.


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