- Analog Design in Nanometer (Fine-Line) CMOS

August 25-28, 2014                                    Deadline for registration: July 14, 2014 registration

MONDAY, August 25

8:30-12:00 am Challenges and Strategies for Mixed-Signal Design Michael Ashburn
1:30-5:00 pm Design of SC Circuits Boris Murmann

TUESDAY, August 26

8:30-10:00 am Design of SC Circuits (Continued) Boris Murmann
10:30-12:00 pm ADC Design for High-Speed Data Communication Boris Murmann
1:30-3:00 pm Substrate Noise Marcel Pelgrom
3:30-5:00 pm Signal Integrity and Monitors Marcel Pelgrom

WEDNESDAY, August 27

8:30-10:00 am FinFets Adrian Ionescu
10:30-12:00 am
& 1:30-5:00 pm
Time-Based Analog Filters and ADCs Pavan Hanumolu

THURSDAY, August 28

8:30-10:00 am System Power Management in nm Technologies Vadim Ivanov
10:30-12:00 am nm CMOS Power Management Circuit Techniques Michiel Steyaert
1:30-5:00 pm Clock Generation Pavan Hanumolu
registration

Abstracts

ANALOG DESIGN IN NANOMETER (FINE-LINE) CMOS
August 25-28, 2014
EPFL Premises, Lausanne, Switzerland

Challenges and Strategies for Mixed-Signal Design 
Michael Ashburn, MediaTek

Deep-submicron CMOS technologies present a host of new challenges in both design and layout.  The course aims to introduce analog/mixed-signal design engineers to modern CMOS technologies and to provide the necessary background and strategies for designing in advanced process nodes.  The lectures include an overview of deep-submicron process technology, device characteristics, and design/layout techniques and examples.

Design of Switched-Capacitor Circuits
Boris Murmann, Stanford University

Switched capacitor (SC) circuits are ubiquitous in CMOS mixed-signal ICs. In this 3-module sequence, we will review the design fundamentals of SC circuits at the transistor level. In the first part we will analyze the imperfections of MOS switches and discuss practical circuit solutions such as clock bootstrapping and bottom plate sampling. The second part will deal with the analysis and simulation of thermal noise in SC circuits. We consider analytical tools for the analysis of noise from the switch network as well as the charge redistribution amplifier, and also discuss the proper simulation setups. Finally, a systematic methodology for the design of the SC circuit’s constituent amplifiers is presented. Using Spice-generated look-up tables that capture the tradeoff between speed (gm/Cgg) and power efficiency (gm/ID), the proposed approach bridges the gap between simulation, hand analysis and Matlab optimization. As a result, amplifiers can be designed for an optimum tradeoff without iterative Spice simulations and “tweaking”.

ADC Design for High-Speed Data Communication
Boris Murmann, Stanford University

As modern electrical and optical communication systems transition toward advanced modulation schemes, there exists a pressing need for power efficient A/D converters operating at tens of gigasamples per second. Within this context, this module will cover relevant circuit- and architecture-level design techniques for high-speed CMOS A/D converters. At the circuit level, we will discuss fundamental challenges in the design of sampling front-ends and voltage comparators, which will also include a review of clock jitter and metastability. At the architecture level, we consider tradeoffs in the design of time-interleaved SAR and flash converters, as well as techniques for the estimation, system-level budgeting and calibration of circuit imperfections.

Substrate Noise
Marcel Pelgrom, Pelgrom Consult

The trend to integrate more functionality in one package has led to ICs with a large number of different functions in one die or one package. Very often these functions pose completely different requirements on the environment they operate in. Control over the mutual interference between these blocks is essential to avoid that a design in the end does not meet the specifications.
Substrate noise is generated, transported and received. In this talk each of these aspects will be discussed, and the effectiveness of several methods to improve the performance will be discussed.

Signal Integrity and Monitors
Marcel Pelgrom, Pelgrom Consult

The increasing complexity of VLSI chips with nanometer feature sizes has reduced the operating margins in digital circuits. Voltage spikes and dips, temperature variations, cross talk, supply and substrate noise, etc impair the power supplies. These variations depend on unforeseen operational conditions and, consequently, chips fail although they passed standard test procedures. Particularly for nanometer CMOS ICs, the large number of metal layers with the increasing metal densities (metal fill), prevents physical probing of the signals for debug purposes.
To enhance observation of important design and technology parameters, such as supply noise, capacitances, temperature, threshold voltage, etc., monitors are embedded within the functional cores. Dedicated monitor circuits have been proposed. This talk reviews signal integrity and shows a concept that deals with these problems without special requirements on technology, design, layout, testing or operation.

FineFets
Adrian Ionescu, EPFL

Abstract to come.

Time-based Analog Filters and ADCs
Pavan K. Hanumolu, University of Illinois

Time-based signal processing is emerging as a viable alternative to analog signal processing traditionally performed in voltage, current, or charge domains. This tutorial discusses time-based techniques to implement analog filters and analog-to-digital converters. After taking a cursory look at analog circuit imperfections in scaled CMOS technologies, the behavior and performance of ring oscillator as a substitute to classical analog integrators will be presented. Both analysis and design methodologies using ring oscillators as key building blocks will be discussed. Case studies of state-of-art time-based analog filters and ADCs will be presented.

System Power Management in nm Technologies
Vadim Ivanov, Texas Instruments

Discussed are the PM circuit techniques for SoC in 90 nm and below processes having multiple digital and analog domains, including main DCDC converter from Li battery using low-voltage switches, any cap stable digital LDO’s with instant reaction on load switching and low noise LDO’s for RF units. Also discussed are precision voltage references with nanopower consumption using low-gain substrate PNPs.

Lnm CMOS Power Management Circuit Techniques
Michiel Steyaert, KU Leuven

In this lecture several power management techniques such as LDO and Capacitive DCDC converters in nanometer technologies are studied. Especially the combination and effects of low voltage nanometer technologies and the required fully integrated voltage conversion techniques are analyzed (the so called source-drain engineering techniques). Also some EMC issues and requirements are briefly discussed. Some design examples of 90nm and 65 nm designs will be discussed.

Clock Generation
Pavan Hanumolu, University of Illinois

Generating precise clocks in nano-scale CMOS technologies is a challenging task. In this tutorial, several architectural- and circuit-level techniques that seek to overcome the detrimental impact of analog circuit imperfections that plague conventional clock generators will be discussed. After a brief overview of the drawbacks of classical analog phase-locked loops (PLLs), the tutorial progresses with the evolutionary presentation of highly digital clock generators. Several case studies of analog enhancement techniques and digital PLLs will be presented.

Scroll to Top